Introduction

I have designed my own take on a retro Motorola 68000-based single-board computer, as seen here. The original version of the board incorporated one megabyte of memory, a common feature in homebrew 68000 SBCs. I wanted access to more memory for my board, but did not want the complexity of using dynamic RAM or the board space involved in adding more static memory. I came across pseudo-static RAM (PSRAM) chips, specifically the IS66WVE4M16EBLL, which internally function as DRAM but employ an SRAM-style interface to the system. Essentially, these chips contain embedded DRAM controllers. It made sense to then build a SIMM module to host these chips so that I could use a standard 72-pin SIMM socket on my single board computer.

Warning

The SIMM module in this repository is completely incompatible with conventional DRAM SIMMs.

The “SRAM SIMM” within this repository uses two of these 4Mx16 PSRAM chips (the BGA parts in the picture above) along with four level shifters for 5V compatibility (the larger TSSOP-48 chips), a voltage regulator (SOT-23-5), and a small amount of logic (the two chips in the middle). The SRAM SIMM implements two 16-bit channels so can be used in 16-bit or 32-bit systems. The module could be useful to other SBC designs that want access to a decent amount of memory but without the complexity of a DRAM controller.

Table of Contents

• Schematic
• Manufacturing Notes
• Pinout
• Use in 16-bit systems
• Use in 32-bit systems
• Sockets
• Acknowledgements
• License

Schematic

This four layer board was created using Kicad version 8.0. The KiCad files are available in this repository.

Click on the schematic to download a PDF version.

Manufacturing Notes

Use these Gerber files to have boards manufactured. Since JLCPCB requires assembled boads to be at least 70mm wide, the board has been panelized with three rows and one column, with rails and fiducials added. I used KiKit to do the panelization using this command, then used the "JLCPCB Fabrication Toolkit" KiCad plugin to generate the Gerbers.

kikit panelize \
    --layout 'grid; rows: 3; cols: 1; vspace: 5mm;' \
    --tabs 'spacing; width: 7mm; spacing: 20mm;' \
    --cuts 'mousebites; drill: 0.6mm; spacing: 0.9mm; offset: -0.3mm' \
    --framing 'frame; width: 5mm;' \
    --tooling '4hole; hoffset: 2.5mm; voffset: 2.5mm; size: 1.5mm' \
    --fiducials '4fid; hoffset: 5mm; voffset: 2.5mm; coppersize: 2mm; opening: 1mm;' \
    --post 'millradius: 1mm' \
    SRAM_SIMM_16MB.kicad_pcb SRAM_SIMM_16MB_panel.kicad_pcb

For assembly at JLCPCB, you will also need to the bom.csv and positions.csv files available in the production directory. When ordering from JLCPCB, be sure to choose the PCB width to be 1.2mm to fit in a standard 72-pin SIMM socket. JLCPCB defaults to 1.6mm on their order page.

Pinout

The pinout supports two 16-bit channels, each with its own chip enable, output enable and dual byte-write enables. The 22-bit non-multiplexed address bus is shared between the channels.

Signal Group	Count
Power & Ground	8
Address Bus	22
Data Bus	32
Control	8
Reserved	2
Total	72

Use in 16-bit systems

Here is an example of how to use this SRAM SIMM in a 16-bit system, taken from my BITSY MK I computer.

• The address bus is shifted by one, so the CPU's A1 is connected to the SRAM SIMM's A0, etc.
• There are two 16-bit data channels, tied together (i.e. D31..D16 is connected to D15..0).
• The two SRAM SIMM chip enables are separately controlled, with one selecting the first channel and the other selecting he second channel. Ensure that only one chip enable is enabled at a time.
• The two SRAM SIMM output enables are tied together with one read signal.
• One system write enable (/WRODD) is connected to one /WE of each channel (/WE0 and /WE2). The other system write enable (/WREVEN) is treated likewise.

Use in 32-bit systems

Here is an example of how to use this SRAM SIMM in a 32-bit system.

• The address bus is shifted by two, so the CPU's A2 to connected to the SRAM SIMM's A0, etc.
• There is one 32-bit data channel, D31..D0.
• The two SRAM SIMM chip enables are tied together with one select signal.
• The two SRAM SIMM output enables are tied together with one read signal.
• The four SRAM SIMM write enables are each separately controlled.

Sockets

The notch on the left side of the SRAM SIMM module picture above is a polarization notch. I've used the module with both left and right polarized sockets.

I've used this vertical socket from Mouser. PEConnectors.com has similar sockets available for less cost than Mouser. There are also lower profile, angled connectors available from various distributors.

Acknowledgements

Thanks go to the creator of this 72-pin SIMM template that I started with.

License

The design in this repository is licensed under CERN-OHL-S version 2 or any later version.