FPU: deliver full architectural FP register to the vector coprocessor (preserve NaN-box for .vf scalars)

[emiliengnr]

Hello, here is a pull request for a bug I found.

Problem

A vector .vf op reads its scalar FP operand from Rocket through the FPU store-data port,
which FPToInt builds by replicating the low element bits across fLen. For the
read_frs1 micro-op at SEW=32 the tag is S, so a NaN-boxed single 0xFFFFFFFF_3f800000
reaches the coprocessor as 0x3f800000_3f800000: the box is overwritten by a copy of the
value. The coprocessor can no longer tell a boxed single from an unboxed register, so it
cannot apply NaN-boxing for a narrow .vf scalar. io.v_sew is the architectural
vtype.vsew, so the coprocessor cannot ask for wider delivery; the fix belongs here.

Fix

Use the max-width tag for the read_frs1 micro-op so the store emits the full
ieee(in.in1) and the box survives:

-      id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
+      id_ctrl.typeTagOut := D

The low bits are unchanged, so no correct result changes. Here typeTagOut feeds only
io.out.bits.store (toint keys on in.fmt(0)) and only for read_frs1, so scalar
stores and fmv.x/fcvt are unaffected. Verified against spike: at SEW=32 a boxed
single passes through and an unboxed double reads as the canonical NaN.

Related: ucb-bar/saturn-vectors#88

This is the delivery-side change the NaN-box check in
ucb-bar/saturn-vectors#88 depends on.
That check inspects the scalar's upper 32 bits, which on stock rocket-chip are a copy of
the low bits, so it wrongly turns boxed singles into NaN. With this patch the coprocessor
sees the real box and the check becomes correct. #88 cannot work without it.