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Merged
fitzgen merged 1 commit into from
Jun 22, 2026
+10 −7
Merged

Tag table.fill/table.copy element stores with table alias regions #13712

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6 changes: 4 additions & 2 deletions crates/cranelift/src/func_environ.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3806,11 +3806,12 @@ impl FuncEnvironment<'_> {
match entity {
CheckedEntity::Table { table, initialized } => {
assert!(!is_pre_interned_funcref);
let region = self.table_alias_region(builder.func, table);
self.emit_table_set(
builder,
table,
elem_addr,
ir::MemFlagsData::trusted(),
ir::MemFlagsData::trusted().with_alias_region(Some(region)),
value,
initialized,
)?
Expand Down Expand Up @@ -4464,11 +4465,12 @@ impl FuncEnvironment<'_> {
};
match dst_entity {
CheckedEntity::Table { table, initialized } => {
let region = this.table_alias_region(builder.func, table);
this.emit_table_set(
builder,
table,
dst,
ir::MemFlagsData::trusted(),
ir::MemFlagsData::trusted().with_alias_region(Some(region)),
val,
initialized,
)?;
Expand Down
3 changes: 2 additions & 1 deletion tests/disas/startup-table-initial-value.wat
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,7 @@
;; function u2415919104:0(i64 vmctx, i64) tail {
;; region0 = 2684354560 "VMTableDefinition+0x0"
;; region1 = 2684354568 "VMTableDefinition+0x8"
;; region2 = 1342177280 "DefinedTable(StaticModuleIndex(0), DefinedTableIndex(0))"
;;
;; block0(v0: i64, v1: i64):
;; v9 = load.i64 notrap aligned region1 v0+56
Expand All @@ -56,7 +57,7 @@
;;
;; block1(v29: i64):
;; v86 = iconst.i32 1
;; store notrap aligned v86, v29 ; v86 = 1
;; store notrap aligned region2 v86, v29 ; v86 = 1
;; v87 = iadd.i64 v18, v81 ; v81 = 36
;; v88 = icmp eq v29, v87
;; v89 = iconst.i64 4
Expand Down
8 changes: 4 additions & 4 deletions tests/disas/table-copy.wat
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Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@
;; block7(v65: i64):
;; @0090 v69 = iconst.i64 1
;; @0090 v70 = bor v65, v69 ; v69 = 1
;; @0090 store notrap aligned v70, v50
;; @0090 store notrap aligned region5 v70, v50
;; @0090 v71 = iconst.i64 8
;; @0090 v72 = iadd.i64 v50, v71 ; v71 = 8
;; @0090 v73 = iconst.i64 8
Expand All @@ -200,7 +200,7 @@
;; block9(v99: i64):
;; @0090 v103 = iconst.i64 1
;; @0090 v104 = bor v99, v103 ; v103 = 1
;; @0090 store notrap aligned v104, v82
;; @0090 store notrap aligned region5 v104, v82
;; @0090 v105 = icmp.i64 eq v84, v35
;; @0090 brif v105, block5, block4(v82, v84, v86)
;;
Expand Down Expand Up @@ -327,7 +327,7 @@
;; block7(v68: i64):
;; @009f v72 = iconst.i64 1
;; @009f v73 = bor v68, v72 ; v72 = 1
;; @009f store notrap aligned v73, v50
;; @009f store notrap aligned region5 v73, v50
;; @009f v74 = iconst.i64 8
;; @009f v75 = iadd.i64 v50, v74 ; v74 = 8
;; @009f v76 = iconst.i64 8
Expand All @@ -346,7 +346,7 @@
;; block9(v105: i64):
;; @009f v109 = iconst.i64 1
;; @009f v110 = bor v105, v109 ; v109 = 1
;; @009f store notrap aligned v110, v85
;; @009f store notrap aligned region5 v110, v85
;; @009f v111 = icmp.i64 eq v87, v35
;; @009f brif v111, block5, block4(v85, v87, v89)
;;
Expand Down
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