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LLM SVA Generator

Overview

This application converts plain-English hardware specifications into SystemVerilog Assertions (SVA). It uses an AI model to read your text descriptions and write the corresponding code automatically.

The tool features a self-correcting agentic loop: if the generated code has syntax errors, the application feeds the Verilator linting errors back to the AI to fix them automatically before saving the final output. It is built to be simple to use, either through an interactive terminal or via file-driven commands.

Prerequisites: Ollama API Key

This application uses Ollama to power its natural language processing capabilities. In order to run the application, you must:

  1. Create an account on the Ollama website.
  2. Generate an API key from your account settings.
  3. Add this API key to your .env configuration file (see Setup Instructions below).

Setup Instructions

1. Installation

Clone the repository and set up a Python virtual environment to keep your dependencies isolated:

git clone <repo-url>
cd llm-sva-generator
python3 -m venv venv
source venv/bin/activate
pip install -r requirements.txt

2. Configuration

Copy the provided environment template to a secure local .env file:

cp .env.example .env

Open .env in a text editor and fill in your Ollama API key:

OLLAMA_API_KEY=your_ollama_api_key_here
OLLAMA_HOST=https://ollama.com
LLM_MODEL=qwen3-coder-next

3. Install Verilator (Optional)

The system uses Verilator to validate whether the generated assertions are syntactically correct.

# Ubuntu/Debian
sudo apt-get install verilator

# macOS
brew install verilator

Note: If you do not install Verilator, you can still run the script using the --dry-run flag to skip validation entirely.

Usage

Ensure your virtual environment is active before running the script.

File-Driven Mode

You can point the tool directly at a textual specification file:

python3 main.py examples/req_ack.txt

Interactive Mode

Run the tool without arguments to enter an interactive session, where you can choose to directly type out specifications or provide a file path to be read:

python3 main.py

Dry Run (Skip Linting)

If Verilator is unavailable, use --dry-run to generate code without validation.

python3 main.py examples/req_ack.txt --dry-run

Agentic AI Architecture

The application operates on an agentic loop. When the user provides a specification, it passes through an LLM to generate the initial SVA code. This code is then validated by Verilator. If linting fails, the errors are collected and sent back to the LLM for corrections until it passes or the retry limit is exhausted.

flowchart TD
    User([User]) -->|Provides Specification| Main[main.py: CLI]
    Main -->|Sends Spec| Generator[generator.py: Orchestration]
    Generator -->|Request SVA| LLM[llm_client.py: API Client]
    
    LLM -->|API Call| Ollama[(Ollama Cloud API)]
    Ollama -->|Returns SVA Code| LLM
    LLM -->|Raw Code| Generator
    
    Generator -->|Submits Code| Validator[validator.py]
    Validator -->|Wraps Code & Runs| Verilator[Verilator Linter]
    Verilator -->|Returns Logs| Validator
    Validator -->|Pass/Fail Result| Generator
    
    Generator -- "If Failed (Retry Loop)" --> LLM
    Generator -- "If Passed or Retries Exhausted" --> Main
    Main -->|Writes Result| Output[(Output .sv File)]
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Application File Details

The codebase is split into specific roles to separate concerns between user interaction, AI prompting, and Verilog validation.

%%{init: { "flowchart": { "curve": "linear" } } }%%
graph LR
    Root["llm-sva-generator"]

    Root --> CLI
    Root --> Core
    Root --> Support

    subgraph CLI["Interface"]
        Main["main.py"]
    end

    subgraph Core["Core Engine"]
        Generator["generator.py"]
        LLM["llm_client.py"]
        Validator["validator.py"]
        Prompts["prompt_templates.py"]
    end

    subgraph Support["Config & Examples"]
        Env[".env"]
        Examples["examples/"]
    end

    Generator --> LLM
    LLM --> Generator
    Generator --> Validator
    Validator --> Generator
    Generator --> Prompts
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About

A simple tool that converts hardware specification text into SystemVerilog Assertions using an LLM.

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