Skip to content

Fix SELRANGE in vf7_wrapper: move VLEN/64 guard to generate level#29

Open
Saksham05oct wants to merge 1 commit into
bsc-loca:mainfrom
Saksham05oct:fix-vf7-selrange
Open

Fix SELRANGE in vf7_wrapper: move VLEN/64 guard to generate level#29
Saksham05oct wants to merge 1 commit into
bsc-loca:mainfrom
Saksham05oct:fix-vf7-selrange

Conversation

@Saksham05oct

Copy link
Copy Markdown

The GEN_VF7 genvar loop runs i over 0..(VLEN/32)-1, but the SEW_64 path sliced src_i[(i*64) +: 64], which is elaborated for every i and indexes outside src_i ([VLEN-1:0]) for i >= VLEN/64 (Verilator SELRANGE at i=2,3 under VLEN=128). Move the (i < VLEN/64) guard to a generate-level if so the 64-bit slice is only elaborated for valid lanes. The SEW_32 assignment is zero-extended explicitly to keep widths matched. Behaviour is unchanged.

The GEN_VF7 genvar loop runs i over 0..(VLEN/32)-1, but the SEW_64 path
sliced src_i[(i*64) +: 64], which is elaborated for every i and indexes
outside src_i ([VLEN-1:0]) for i >= VLEN/64 (Verilator SELRANGE at i=2,3
under VLEN=128). Move the (i < VLEN/64) guard to a generate-level if so the
64-bit slice is only elaborated for valid lanes. The SEW_32 assignment is
zero-extended explicitly to keep widths matched. Behaviour is unchanged.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant