Fix width mismatches in riscv_pkg and drac_pkg#27
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MSTATUS32_WPRI was declared [64:0] instead of [63:0]. DCACHE_BUS_WIDTH was a 10-bit parameter, propagating into width warnings on divisions. VMAXELEM and DCACHE_MAXELEM are 7-bit parameters initialized from 32-bit divisions, now cast explicitly. The DracCfg memory-map literals were 40-bit constants assigned to PHY_ADDR_SIZE-wide fields inside NrMaxRules-sized arrays; they are now explicitly sized and padded. All configuration values are unchanged; the previously implicit truncations/extensions are now explicit, removing the package warnings that appeared in the lint output of every file.
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Follow-up to the lint work in #22: width mismatches in the shared packages showed up in the lint output of every single file, hiding real per-file warnings.
riscv_pkg.sv:MSTATUS32_WPRIwas[64:0](65 bits) — typo, every neighbouring constant is[63:0].drac_pkg.sv:DCACHE_BUS_WIDTHwas declared as a 10-bit literal (10'd512), propagating width warnings into every expression using it.drac_pkg.sv:VMAXELEM/DCACHE_MAXELEMare 7-bit params initialized from 32-bit divisions — now cast explicitly.drac_pkg.sv: theDracCfgmemory-map literals were 40-bit constants assigned toPHY_ADDR_SIZE-wide fields insideNrMaxRules-sized arrays — now explicitly sized and padded. Notably,InitMappedEnd's40'h3fffffffffneeds 38 bits and was silently truncating atPHY_ADDR_SIZE=32; the truncation is now explicit.Configuration values are unchanged in every case. Verified on Verilator 5.048 and 5.020: the package warnings no longer appear when linting any RTL file.
Fixes #26