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masc#440 publishes a register handle per row and a class handle per class on aarch64 and x86, so the aarch64 axes name the sve class through Z_CLASS in place of position 12. mink 0fa33d8 and std 8d0abcb already match masc's pins.
octalide
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October 17, 2026 00:53
octalide
enabled auto-merge
October 17, 2026 00:53
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Closes #357
What
Takes masc dev 24126ea (masc#440, carrying masc #412, #414, #415 and #416) on the same mink 0fa33d8 and std 8d0abcb as dev. Both match masc's gitlinks, and masc did not move MACH_REF, so it stays at 1ea24dc.
Ported Consumer changes between masc ad1c60c and 24126ea:
src/target/register/aarch64/axes.machnames its SVE class as?aarch64_register.CLASSES[aarch64_register.Z_CLASS]in place of position 12. riscv handles are unchanged.field.Refusalgainsreach), feat(#362): thread-local and GOT access on x86-64 and AArch64 #414 (Reader.sequence, bare riscv symbols refused), feat(#408): jump tables on AArch64 #412 (x86LEVELSstate) and Select thread-local access on x86-64 windows through the TLS index #416 (Set.locals): mirl builds no mascRefusalorReaderliteral, itsSetliterals leavelocalsout and so get none, and it reads noLEVELSrow. Nothing to port.Ran
mach check . -a '*'andmach build . -a cliclean, with mach built at MACH_REF through bootstrap.sh.Moved to #342
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