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Nans.propagate carries the nan an invalid operation gives where no operand is one, positive canonical or negative. the folder gives it, and x86-64's sse2 rows state the negative quiet nan, the real indefinite.
a virtual half of a tie is named through the view its position takes of its class, so a two-address row over a narrower view of a value stands. the address source builds a memory operand from a base, an index scaled by a literal or derived power of two, a displacement or a symbol, a segment and a pc-relative mode, admitted by the row's memory position.
a reader of a register lying within either end of the swap reads the register of its class at the same place within the other, through masc's within. the bits of the source no pending destination covers must hold no value past the copy, and every pending pair is tried for the swap.
…h shape a call keeps a register lying within a wholly kept one and clobbers one holding a kept one, refusing only a straddle. a frame past a page under a row whose prologue calls a probe routine moves through the frame code's probe step, the routine declared by the convention lowering. windows' unwind codes take one fixed allocation, the saves and a frame pointer set at most 240 bytes above the stack pointer.
3 tasks done
A loop step names the memory at the address a register operand of the loop holds (lrow.Source.address), as x86's lock cmpxchg names its destination. An implicit register a step reads is written for certain by an earlier step's write through a fixed register, so lrow.check takes the register file. A built address takes a fixed register as its base, as the string moves address through rdi and rsi, and a materialisation rule builds an address of its constant alone.
# Conflicts: # src/machine/compile.mach
The x86-64 members carry their convention rows. SysV classifies each eightbyte as clang does, counts the vector registers of a variadic call in al and takes the whole value to the stack when its registers run out. Win64 passes by position, a variadic float in both registers, an i128 by reference and returns it in xmm0, keeps xmm6 to xmm15, and probes a page through __chkstk with the seh prologue shape. The division widths are 32 and 64: the byte and word forms divide ah:al and dx:ax, which no rule splits, so the narrow legalisation widens a byte or a word division and keeps its traps.
The x86-64 table holds integers, conditions and pointers in gpr64 and floats and vectors in xmm, naming each row's view of one location, so a value read at several widths is never copied. Compares fuse with the jcc, setcc or cmov that reads them, division, high products and variable shifts go through masc's fixed operands, and loads and stores fold [b + i*s + d] and rip-relative symbols. Float to integer saturates branch-free. sse4.1's pmovsx, pmovzx, pmulld and roundss are taken where admitted, with punpck and pmuludq below. Atomics are lock xadd, xchg and cmpxchg, and cas loops for the rest. The frame code moves through lea and the page probe through __chkstk. xchg swaps two general registers at each view. The record joins masc's x86 set in the register family's registry.
The example lane runs x86_64 linux gnu beside the riscv lanes, its __mirl_exit the exit system call, and windows has one through kernel32's ExitProcess for a link with mink. The lane script takes an architecture's own exit stub where it has one. The comments that said masc serves x86-64 with no set are corrected.
The nodes, tests, sources and expansions of the x86 table stand in their own groups, as RISC-V's do, each group of rules and of their expansions under a comment saying what it selects, and the three forms of a compare are named by their operand.
octalide
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October 17, 2026 01:51
octalide
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October 17, 2026 01:53
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Closes #43
What
x86-64 end to end: the SysV and Win64 convention rows, the x86 Isa record (selection table, hooks,
casloops, frame code, moves, declared opcodes), the NaN default and saturating float to integer conversion. Also the shared machinery the target needs: memory operands built by rules, loops that address memory, swaps through partial readers, containment-aware clobbers, and the Win64 page probe and SEH prologue shape.Plan, one commit or more each, shared changes kept apart from the x86 rows:
Nans.propagatestates its default NaN (Default). x86-64 is propagate with the negative quiet NaN, and the folder's invalid operation gives it.Source.address(Addressed,Factor, a fixed base for string moves) andinstruction.fits_address. Tie halves take views.storage.liesandstorage.counterpart, andswap_anyin copy lowering.Kept{xmm6,128}keeps xmm6 and clobbers ymm6. Page probes go through a helper (Code.probe,Step.probe,lay.Request.helper), and the SEH prologue shape.lrow.Source.address). An explicit fixed write counts as the write an implicit read needs, solrow.checktakes the register file.x86/abi.mach): SysV eightbyte classification with the AL count, Win64 positional slots, variadic floats in both registers, i128 by reference and returned in xmm0.Choices the issue did not settle:
jcc,setccorcmovthat reads it in one expansion. That is "cmp then jcc in the FLAGS class" as far as the current engine allows.ah:al.mfence. An expansion cannot be empty, and a compiler-only barrier has no row.func.addrare rip-relativelea. The x86 address model is none, so the hooks read the symbol directly and leave TLS unselected.__chkstkis called asmov eax, n; call __chkstk; sub rsp, rax, declared by the abi legalisation when a function is defined.Limits
fma.allocaprobing._startwith the stack 16-byte aligned, so the frames below the example stubs are 8 off. The x86 frame code uses unaligned xmm moves.Moved to #342
[b+i*4+d], a call's clobbers from its row, xmm6 surviving and the ymm upper clobbered.xchgbreaking a copy cycle.stnever ends an overlapping value, andmm3ends only itself.Ran locally:
mach check . -a '*',mach build . -a cliandmach fmt --check ..Checklist