[Codegen][CPU] Materialize data-tiled encodings to inner_tiled.#1
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[Codegen][CPU] Materialize data-tiled encodings to inner_tiled.#1bjacob wants to merge 1 commit into
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When a target sets `enable_inner_tiled = true`, lower matmuls with encodings to `iree_codegen.inner_tiled` whose kind is a CPU `data_tiled_mma_layout`, instead of `linalg.mmt4d`. The intrinsic and its orientation (`transposed_intrinsic`) are chosen jointly by a small cost model that maximizes "useful ops" per invocation (charging an intrinsic for the padding it would force along statically narrow M/N), with the intrinsic's raw M*N*K as tiebreaker. Unroll factors are hard-coded to `intrinsics_m = intrinsics_n = 1` for now; a follow-up commit introduces the register-budget/arithmetic- intensity cost model that picks better values. Also: - Add the AVX2+FMA f32 intrinsic (`MMA_X86_AVX2_FMA_1x8x1_F32_F32`) to enabling writing additional tests. - Have MaterializeEncodingPatterns emit a clean op-level error if a layout lowering returns nullptr, rather than segfaulting. Made-with: Cursor Signed-off-by: Benoit Jacob <jacob.benoit.1@gmail.com>
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When a target sets
enable_inner_tiled = true, lower matmuls with encodings toiree_codegen.inner_tiledwhose kind is a CPUdata_tiled_mma_layout, instead oflinalg.mmt4d.The intrinsic and its orientation (
transposed_intrinsic) are chosen jointly by a small cost model that maximizes "useful ops" per invocation (charging an intrinsic for the padding it would force along statically narrow M/N), with the intrinsic's raw MNK as tiebreaker.Unroll factors are hard-coded to
intrinsics_m = intrinsics_n = 1for now; a follow-up commit introduces the register-budget/arithmetic- intensity cost model that picks better values.Also:
MMA_X86_AVX2_FMA_1x8x1_F32_F32) to enabling writing additional tests.Made-with: Cursor