Simulator-based labs on caching, memory hierarchy, DRAM, memory scheduling and prefetching — an independent, from-skeleton implementation of 227-2210-00L Computer Architecture (ETH Zürich, Fall 2022, Prof. Onur Mutlu), part of a csdiy.wiki full-catalog build.
This repo implements the microarchitecture-simulator assignments of ETH Zürich's
Computer Architecture course. Starting from the course-provided cycle-accurate
MIPS timing simulator, it adds an L1 cache model, an L2 + FR-FCFS DRAM memory
hierarchy, two academic DRAM scheduling policies in Ramulator, and an L2
prefetcher in ChampSim — each verified with the course's own test harness or the
simulator's own metrics, with measured results captured under results/.
| Lab | What it implements | Result (measured) |
|---|---|---|
| Lab 1 — Caching | L1 I/D cache timing on the MIPS pipeline + design-space sweep | 92/92 inputs REGISTER CONTENTS OK; primes.x D-hit 55%→99.5% as size 4KB→64KB |
| Lab 2 — Memory Hierarchy | Unified L2 cache (16 MSHRs) + cycle-accurate FR-FCFS DRAM | 92/92 OK; 42.55% L2 hits (1KB L1); DRAM row-hits 2040/2052 on primes.x |
| Lab 4 — Memory Scheduling | ATLAS & BLISS schedulers in Ramulator | FCFS worst (IT 3.438); ATLAS best-tier (IT 3.466, max-slowdown 1.003) |
| Lab 5 — Prefetcher (bonus) | L2C stream prefetcher in ChampSim | stream +30.3% IPC (0.206→0.269, 100% accuracy) vs next_line +13.6% |
| Lab 3 — PIM/UPMEM | AXPY DPU kernel + host transfers | AXPY kernel verified vs host reference (needs UPMEM SDK/HW to run) — partial |
| Lab 6 — Multicore/MESI (bonus) | 4-core MESI coherence | tests imported + design documented — partial |
Full numbers: results/lab1_cache_sweep.csv, results/lab2_memsys_results.txt,
results/lab4_scheduler_eval.txt, results/lab5_prefetcher_eval.txt,
results/lab3_axpy_kernel_check.txt.
- Lab 1 — Simulating and Exploring Cache Behavior — L1 I-cache (8KB/4-way) and D-cache (64KB/8-way) with 50-cycle miss timing, LRU/MRU/RANDOM/FIFO replacement and MRU/LIP/BIP insertion; cache design-space exploration.
- Lab 2 — Memory Hierarchy — unified 256KB/16-way L2 with 16 MSHRs, plus a cycle-accurate open-row FR-FCFS DRAM (banks, row buffers, bus/bank timing) replacing Lab 1's constant miss latency.
- Lab 4 — Memory Request Scheduling — ATLAS (least-attained-service) and BLISS (blacklisting) memory schedulers added to Ramulator, evaluated for instruction throughput and maximum slowdown.
- Lab 5 — Prefetcher Design (bonus) — a multi-way L2C stream prefetcher in ChampSim, out-performing the provided next_line / ip_stride baselines.
- [~] Lab 3 — Programming a Real PIM Architecture — UPMEM AXPY kernel + host code fully written; documented partial (proprietary UPMEM SDK/hardware unavailable on this CPU box).
- [~] Lab 6 — Multicore and Cache Coherence (bonus) — coherence tests imported and MESI design documented; documented partial.
ethz-computer-architecture/
├── lab1-caching/ # MIPS sim + L1 cache model (src/cache.*, tools/sweep.py)
├── lab2-memory-hierarchy/ # + L2 cache & FR-FCFS DRAM (src/memsys.*)
├── lab3-pim/ # UPMEM AXPY kernel + host (documented partial)
├── lab4-memory-scheduling/ # Ramulator + ATLAS/BLISS (ramulator/src/Scheduler.h)
├── lab5-prefetcher/ # ChampSim + stream prefetcher (partly bonus)
├── lab6-multicore-coherence/# MESI tests + design (documented partial)
├── results/ # measured outputs (CSV / txt)
└── LICENSE
Everything runs on WSL2 Ubuntu (the course targets Linux) with gcc/g++
and python3; no GPU needed.
# Lab 1 — cache model
cd lab1-caching && make && python3 run.py # 92/92 REGISTER CONTENTS OK
python3 tools/sweep.py # -> results/lab1_cache_sweep.csv
# Lab 2 — L2 + DRAM
cd lab2-memory-hierarchy && make && python3 run.py
# Lab 4 — Ramulator ATLAS/BLISS
cd lab4-memory-scheduling/ramulator && make -j
../scripts/download_traces.sh # 110MB trace (gitignored)
../scripts/evaluate_schedulers.sh # -> results/lab4_scheduler_eval.txt
# Lab 5 — ChampSim stream prefetcher
cd lab5-prefetcher/champsim && ./build_champsim.sh stream
../scripts/run_eval.sh # -> results/lab5_prefetcher_eval.txt- Labs 1 & 2 use the course's own
run.pyharness, which drives the simulator (go / rdump / quit) and compares every register/PC/HI/LO against a no-cache baseline: 92/92 inputs pass for both labs. Cache/L2/DRAM timing stats are printed to stderr and captured toresults/. - Lab 4 uses Ramulator's own statistics (
record_cycs/record_instsper core) to compute instruction throughput and max slowdown across schedulers. - Lab 5 uses ChampSim's own IPC and prefetch-useful/useless counters.
- Lab 3 AXPY kernel arithmetic is checked against the host reference in pure
C (
lab3-pim/axpy_kernel_check.c).
C (MIPS timing simulator, cache & memory-system models), C++11 (Ramulator, ChampSim), Python 3 (test harness & sweep drivers), MIPS-32 assembly (test inputs), WSL2/Linux, gcc/g++ 13.
- Modelling cache/memory timing in a cycle-driven simulator without changing architectural (functional) correctness — stalls as delayed op transfer.
- The full L1→L2→DRAM path: MSHRs, open-row policy, FR-FCFS scheduling, and bus/bank resource reservation for a cycle-accurate DRAM.
- Application-aware DRAM scheduling: least-attained-service (ATLAS) vs blacklisting (BLISS), and their throughput/fairness trade-offs.
- Prefetcher design: stream vs stride vs next-line, and measuring coverage, accuracy and IPC impact.
Based on the assignments of Computer Architecture (227-2210-00L) by
Prof. Onur Mutlu and the SAFARI Research Group at ETH Zürich
(course site: https://safari.ethz.ch/architecture/fall2022/). The base MIPS
timing simulator is by Chris Fallin (2012). Ramulator and ChampSim are
third-party simulators redistributed under their own MIT licenses (see each
subdirectory's LICENSE). This repository is an independent educational
reimplementation; all course materials and specifications belong to their
original authors. Original code here is released under the MIT License.