M68K emulation for ARM
In order to build Emu68 several tools are necessary. The first one is of course git, which will be used to clone the repository. Further, cmake will be used to configure the build. Firmware, if required, will be downloaded by cmake during project configure phase, here, either curl or wget will be used. Finally, an AArch64 or AArch32 toolchain will be necessary.
Make sure your package repository is up to date
sudo apt-get updateSubsequently install the build-essential package as well as the cross-compiler for the target you want to build.
sudo apt-get install build-essential gcc-arm-none-eabi gcc-aarch64-linux-gnu g++-aarch64-linux-gnuFor AArch64 builds (TARGET=raspi64, TARGET=pbpro, TARGET=virt) one more setup step is required. The AArch64 architecture allows bi-endian operation, but the majority of the world is focusing on little-endian format as the native one. The cross-compiler provided by Ubuntu is not an exception and it defaults to little-endian systems. Furthermore, it lacks one big-endian relevant header which will need to be fixed now
sudo cp /usr/aarch64-linux-gnu/include/gnu/stubs-lp64.h /usr/aarch64-linux-gnu/include/gnu/stubs-lp64_be.hOne might wonder how it could work if a little-endian header is taken for the big-endian target. Well, in this case it is fully possible - this file is almost empty. At this point everything is configured properly and building of Emu68 can start. First, clone the repository
git clone https://github.com/michalsc/Emu68.gitAfter entering the Emu68 directory created by git, one need to pull the submodules
git submodule update --init --recursiveNow, create build directory and install directory, enter the build directory
mkdir build install
cd buildFinally, configure the cmake project. For the restored 32-bit Raspberry Pi target:
cmake .. -DCMAKE_INSTALL_PREFIX=../install -DTARGET=raspi \
-DCMAKE_TOOLCHAIN_FILE=../toolchains/arm-elf.cmakeFor a 64-bit Raspberry Pi PiStorm build:
cmake .. -DCMAKE_INSTALL_PREFIX=../install -DTARGET=raspi64 -DVARIANT=pistorm \
-DCMAKE_TOOLCHAIN_FILE=../toolchains/aarch64-linux-gnu.cmakeShould you prefer a 64-bit Raspberry Pi build which works in bare metal but does not require PiStorm board, remove the -DVARIANT=pistorm from the second line. If you prefer to not use the toolchain file, you need to specify your preferred compiler by yourself, e.g.
CC=aarch64-linux-gnu-gcc CXX=aarch64-linux-gnu-g++ cmake .. -DCMAKE_INSTALL_PREFIX=../install \
-DTARGET=raspi64 -DVARIANT=pistormDuring configuration process cmake will fetch the most recent RaspberryPi firmware by itself. After the configuration is completed, build and install from that configured directory:
cmake --build . -j$(nproc)
cmake --install .Now, build process is completed. Copy the contents of the install directory onto FAT32 or FAT16 formatted SD card. Your Emu68 build is completed.
If you switch toolchains or accidentally configure the build directory with your host compiler, re-run CMake from a clean build directory. TARGET=raspi must use the ARM bare-metal toolchain file:
cmake -S . -B build-arm32 -DTARGET=raspi \
-DCMAKE_TOOLCHAIN_FILE=toolchains/arm-elf.cmake
cmake --build build-arm32 -j$(nproc)
cmake --install build-arm32For the ARM32 PiStorm variant, configure the same ARM bare-metal target with -DVARIANT=pistorm:
cmake -S . -B build-arm32-pistorm -DTARGET=raspi -DVARIANT=pistorm \
-DCMAKE_TOOLCHAIN_FILE=toolchains/arm-elf.cmake
cmake --build build-arm32-pistorm -j$(nproc)
cmake --install build-arm32-pistormThe repository root also provides a convenience wrapper for that supported ARM32 flow:
make
make installThe restored TARGET=raspi path includes a bounded QEMU smoke test for early ARM32 bring-up:
scripts/run-qemu-raspi32-smoke.shThis helper injects a minimal device tree, boot shim, and valid one-block HUNK payload on top of the raspi2b machine so the bare-metal ARM32 image can execute translated m68k code under the JIT. The default payload runs moveq #42,d0; rts, and the harness checks that execution returns with D0 = 0x0000002a. Set EMU68_QEMU_PAYLOAD=loop10 to run a small branch loop that returns with D0 = 0x0000000a. Use EMU68_QEMU_TIMEOUT=<seconds> to extend the observation window, for example:
EMU68_QEMU_TIMEOUT=12 scripts/run-qemu-raspi32-smoke.shSet EMU68_QEMU_PAYLOAD=bsr4 to cover an inlined bsr/rts subroutine path that returns with D0 = 0x00000004, EMU68_QEMU_PAYLOAD=stack42 to cover a translated stack push/pop round-trip that still returns D0 = 0x0000002a, EMU68_QEMU_PAYLOAD=a0mem42 to cover an A0 post-increment/pre-decrement memory round-trip against the framebuffer base while still returning D0 = 0x0000002a, EMU68_QEMU_PAYLOAD=pea_a0 to cover PEA (A0) plus stack pop, which returns D0 = 0x3c100000 and can also assert that A7 returns to 0x3f7ff000, EMU68_QEMU_PAYLOAD=cmpiz42 to cover cmpi.b #$2a, d0 and assert the final SR = ..Z.. zero-flag state, EMU68_QEMU_PAYLOAD=cmpibeq7 to cover cmpi.b #$2a, d0; beq and assert that the taken branch returns D0 = 0x00000007, EMU68_QEMU_PAYLOAD=dbf3 to cover a three-iteration dbra d1,<loop> countdown that returns D0 = 0x00000003 and leaves D1 = 0x0000ffff, EMU68_QEMU_PAYLOAD=dbne9 to cover the complementary dbne d1,<skip> fallthrough path where the condition is already true, returning D0 = 0x00000009 with D1 = 0x00000002 unchanged, EMU68_QEMU_PAYLOAD=dbt7 to cover the dbt no-op case, which ignores the displacement, falls through, and returns D0 = 0x00000007 while preserving D1 = 0x00000002, EMU68_QEMU_PAYLOAD=snememff to cover sne.b (a0) storing 0xff through the memory-destination Scc path and then reading it back, EMU68_QEMU_PAYLOAD=stmemff to cover the unconditional st.b (a0) fast path storing 0xff, EMU68_QEMU_PAYLOAD=sfmem00 to cover the unconditional sf.b (a0) fast path storing 0x00, EMU68_QEMU_PAYLOAD=sneregff and EMU68_QEMU_PAYLOAD=snereg00 to cover the conditional sne d0 register path with both true and false outcomes, EMU68_QEMU_PAYLOAD=stregff and EMU68_QEMU_PAYLOAD=sfreg00 to cover the unconditional st d0 and sf d0 register fast paths, EMU68_QEMU_PAYLOAD=trapf_w8, EMU68_QEMU_PAYLOAD=trapf_l9, and EMU68_QEMU_PAYLOAD=trapf_n11 to cover the non-trapping trapf word, long, and no-operand forms, EMU68_QEMU_PAYLOAD=movecvbr15 to cover the standalone ARM32 movec a1,vbr path and leave VBR = 0x3f6fefb4, EMU68_QEMU_PAYLOAD=moveuspfb to cover both privileged ARM32 move a0,usp and move usp,a0, returning D0 = 0x3c100000 while keeping active A7 = 0x3f7ff000, EMU68_QEMU_PAYLOAD=movesr2000 to cover privileged ARM32 move sr,d0, returning D0 = 0x00002700 while leaving active A7 = 0x3f7ff000, EMU68_QEMU_PAYLOAD=movetosr2004 to cover privileged ARM32 move #$2004,sr, returning D0 = 0x00002004 and proving that SEQ sees the injected Z flag by leaving D1 = 0x000002ff with active A7 = 0x3f7ff000, EMU68_QEMU_PAYLOAD=moveccr04 to cover ARM32 move d0,ccr plus move ccr,d0, returning D0 = 0x00000004 and proving that SEQ sees the injected Z flag by leaving D1 = 0x000002ff, EMU68_QEMU_PAYLOAD=nbcd96 to cover register-form ARM32 nbcd d0, returning D0 = 0x00000096 with D1 = 0x00000011, EMU68_QEMU_PAYLOAD=nbcd90h to cover the ARM32 nbcd d0 high-digit carry path on 0x10 -> 0x90, returning D0 = 0x00000090 with D1 = 0x00000011, EMU68_QEMU_PAYLOAD=nbcd0z to cover the zero-result nbcd d0 path that preserves an incoming Z flag, returning D0 = 0x00000000 with D1 = 0x000000ff and D2 = 0x00000004, EMU68_QEMU_PAYLOAD=nbcd99x to cover the ARM32 X-input nbcd d0 path after move d1,ccr, returning D0 = 0x00000099 with D1 = 0x00000011, EMU68_QEMU_PAYLOAD=nbcdpre96 to cover the -(a0) memory NBCD path and restore A0 = 0x3c100000 after reading back 0x96, EMU68_QEMU_PAYLOAD=abcd34 to cover register-form ARM32 abcd d0,d1, returning D1 = 0x00000034 with D2 = 0x00000000, EMU68_QEMU_PAYLOAD=abcd00x to cover the ARM32 X-input register path on 0x00 + 0x99 + X, returning D1 = 0x00000000 with D2 = 0x00000015, EMU68_QEMU_PAYLOAD=abcdpre1 to cover the -(a0),-(a1) memory ABCD path seeded with two zero bytes plus an incoming X, returning D0 = 0x000000ff while leaving A1 = 0x3c100000, EMU68_QEMU_PAYLOAD=packd1234, EMU68_QEMU_PAYLOAD=packd1239, and EMU68_QEMU_PAYLOAD=packd1231 to cover ARM32 pack d0,d1,#<adjustment> with zero, positive, and negative adjustments, leaving D1 = 0x00000234, 0x00000239, and 0x00000231, EMU68_QEMU_PAYLOAD=unpkd1304, EMU68_QEMU_PAYLOAD=unpkd1309, and EMU68_QEMU_PAYLOAD=unpkd1301 to cover the matching unpk d0,d1,#<adjustment> forms and leave D1 = 0x00000304, 0x00000309, and 0x00000301, EMU68_QEMU_PAYLOAD=trapt13 to cover a taken trapt path that programs VBR with movec, builds an in-HUNK vector entry, returns through a real ARM32 rte, and then exits with D0 = 0x0000000d while restoring A7 = 0x3f7ff000, EMU68_QEMU_PAYLOAD=trapne14 to cover the conditional taken trapne path through the same vector machinery and return D0 = 0x0000000e with the same final A7 restoration, EMU68_QEMU_PAYLOAD=casb_ok21 and EMU68_QEMU_PAYLOAD=casb_fail13 to cover ARM32 cas.b d0,d1,(a0) on both the success and compare-register writeback paths, EMU68_QEMU_PAYLOAD=casw_ok5678 and EMU68_QEMU_PAYLOAD=casw_fail1357 to cover the aligned ARM32 cas.w store and compare-register writeback paths, EMU68_QEMU_PAYLOAD=casl_ok89abcdef and EMU68_QEMU_PAYLOAD=casl_fail13579bdf to cover the aligned ARM32 cas.l store and compare-register writeback paths, and EMU68_QEMU_PAYLOAD=cas2w_ok2244, EMU68_QEMU_PAYLOAD=cas2w_fail3333, EMU68_QEMU_PAYLOAD=cas2l_ok22444444, and EMU68_QEMU_PAYLOAD=cas2l_fail3333 to cover paired ARM32 cas2.w success and second-operand mismatch/writeback plus paired ARM32 cas2.l success and second-operand mismatch/writeback, EMU68_QEMU_PAYLOAD=addqb79, EMU68_QEMU_PAYLOAD=subqb77, EMU68_QEMU_PAYLOAD=addqw0000, EMU68_QEMU_PAYLOAD=subqwffff, EMU68_QEMU_PAYLOAD=addqa8, and EMU68_QEMU_PAYLOAD=subqa4 to cover ADDQ/SUBQ byte, word, and address-register forms in the ARM32 line-5 translator, EMU68_QEMU_PAYLOAD=addqb_mem1 and EMU68_QEMU_PAYLOAD=subqb_mem1 to cover the direct byte-memory (A0) quick-arithmetic path, EMU68_QEMU_PAYLOAD=addqb_postinc, EMU68_QEMU_PAYLOAD=subqb_postinc, EMU68_QEMU_PAYLOAD=addqb_predec, and EMU68_QEMU_PAYLOAD=subqb_predec to cover the byte-sized memory (A0)+ and -(A0) quick-arithmetic paths, EMU68_QEMU_PAYLOAD=addqb_a7_postinc, EMU68_QEMU_PAYLOAD=subqb_a7_postinc, EMU68_QEMU_PAYLOAD=addqb_a7_predec, and EMU68_QEMU_PAYLOAD=subqb_a7_predec to cover the byte-sized (A7)+ and -(A7) stack-pointer special case, which restores A7 to 0x3f7ff000 after the translated round-trip, EMU68_QEMU_PAYLOAD=addql_mem1, EMU68_QEMU_PAYLOAD=subql_mem1, EMU68_QEMU_PAYLOAD=addql_postinc, EMU68_QEMU_PAYLOAD=subql_postinc, EMU68_QEMU_PAYLOAD=addql_predec, and EMU68_QEMU_PAYLOAD=subql_predec to cover the 32-bit memory ADDQ/SUBQ paths for direct (A0), (A0)+, and -(A0) operands, and EMU68_QEMU_PAYLOAD=addqw_mem1, EMU68_QEMU_PAYLOAD=subqw_mem1, EMU68_QEMU_PAYLOAD=addqw_postinc, EMU68_QEMU_PAYLOAD=subqw_postinc, EMU68_QEMU_PAYLOAD=addqw_predec, and EMU68_QEMU_PAYLOAD=subqw_predec to cover the corresponding 16-bit memory paths. The register Scc tests preserve the upper 24 bits and return D0 = 0x123456ff or D0 = 0x12345600, the trapf tests prove PC advancement by returning D0 = 0x00000008, 0x00000009, and 0x0000000b, the movec, move usp, move sr, move to sr, move ccr, nbcd, abcd, pack, unpk, taken TRAPcc, CAS, and CAS2 tests prove that ARM32 now writes VBR correctly, routes through a movec-programmed in-HUNK vector handler with a real rte return, transfers USP without disturbing the active supervisor stack, exposes the supervisor SR word through the translated MOVE from SR path, updates the live supervisor SR through the translated MOVE to SR path, updates live condition evaluation through the translated CCR paths, preserves Z across the zero-result NBCD and carry-out ABCD cases, carries X into both decimal negation and decimal addition paths, handles the predecrement memory NBCD and ABCD forms, covers the low-nibble-zero high-digit NBCD correction path, performs register-form BCD pack/unpack across zero, positive, and negative adjustment words without falling back to the old undefined-instruction stub, atomically swaps byte, word, and long values through translated CAS, and preserves compare-register writeback and paired-memory semantics through translated CAS2, the quick byte tests preserve upper bits while returning D0 = 0x12345679 and 0x12345677, the word tests assert SR = X.Z.C and SR = XN..C on D0 = 0x12340000 and 0x1234ffff, the address-register tests prove A0 updates alongside D0 = 0x3c100008 and 0x3c0ffffc, and the memory quick-arithmetic tests round-trip through translated loads and stores to return D0 = 0x000000ff or 0x00000001 while restoring A0 = 0x3c100000, including the direct byte-memory case, the byte-sized A7 update-by-2 special case, and the separate 16-bit and 32-bit memory paths. By default the smoke test treats [JIT] Back from translated code and the payload-specific result marker as the success conditions, then exits cleanly on the bounded timeout. Override them with EMU68_QEMU_EXPECT=<text> and EMU68_QEMU_EXPECT_RESULT=<text> if you want to probe a different boot stage or payload result. Use EMU68_QEMU_BOOTARGS="<args>" to exercise specific ARM32 boot-time paths such as enable_cache, debug, or disassemble without editing the checked-in DTS template, EMU68_QEMU_EXPECT_EXTRA=<text> to require one additional log marker anywhere in the run, and EMU68_QEMU_EXPECT_POST=<text> to require a marker after the main success marker, which is useful for final-state checks like restored A0 or A7.
The ARM32 PiStorm QEMU path now also accepts the AArch64-style swap_df0_with_df1, swap_df0_with_df2, and swap_df0_with_df3 bootargs for the minimal CIA spoof path, plus move_slow_to_chip and block_c0 for the same slow-RAM/trapdoor layout policy that the AArch64 PiStorm runtime already exposes.
The CAS2 coverage now also includes EMU68_QEMU_PAYLOAD=cas2w_fail5555 and EMU68_QEMU_PAYLOAD=cas2l_fail5555 to exercise the distinct first-operand mismatch/writeback branch, proving that ARM32 reloads both compare registers from memory while leaving the paired store path untouched.
The CAS coverage now also includes EMU68_QEMU_PAYLOAD=casb_post_ok21, EMU68_QEMU_PAYLOAD=casb_post_fail13, EMU68_QEMU_PAYLOAD=casb_pre_ok21, and EMU68_QEMU_PAYLOAD=casb_pre_fail13 to exercise byte CAS through the separate (A0)+ and -(A0) auto-update paths on both the store and compare-register writeback branches.
That same CAS block now also includes EMU68_QEMU_PAYLOAD=casw_post_ok5678, EMU68_QEMU_PAYLOAD=casw_post_fail1357, EMU68_QEMU_PAYLOAD=casw_pre_ok5678, and EMU68_QEMU_PAYLOAD=casw_pre_fail1357 to cover the word-size auto-update paths and confirm the +2 / -2 address updates alongside store and writeback behavior.
The longword CAS coverage now also includes EMU68_QEMU_PAYLOAD=casl_post_ok89abcdef, EMU68_QEMU_PAYLOAD=casl_post_fail13579bdf, EMU68_QEMU_PAYLOAD=casl_pre_ok89abcdef, and EMU68_QEMU_PAYLOAD=casl_pre_fail13579bdf to cover the separate (A0)+ and -(A0) long-size auto-update paths and confirm the +4 / -4 address updates on both the store and compare-register writeback branches.
The same CAS block now also includes EMU68_QEMU_PAYLOAD=casw_mis_ok5678, EMU68_QEMU_PAYLOAD=casw_mis_fail1357, EMU68_QEMU_PAYLOAD=casl_mis_ok89abcdef, and EMU68_QEMU_PAYLOAD=casl_mis_fail13579bdf to force the misaligned word and longword paths through the ARM32 CAS_UNSAFE implementation and confirm that compare-register writeback and memory updates still behave correctly at odd and non-4-byte-aligned addresses.
The MULDIV coverage now also includes EMU68_QEMU_PAYLOAD=mulumempost42, EMU68_QEMU_PAYLOAD=mulsmempost42, EMU68_QEMU_PAYLOAD=mulumempre42, and EMU68_QEMU_PAYLOAD=mulsmempre42 to exercise MULU.W and MULS.W through (A0)+ and -(A0) and confirm the +2 / -2 A0 updates alongside the 32-bit product.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumempost5, EMU68_QEMU_PAYLOAD=divsmempostfffb, EMU68_QEMU_PAYLOAD=divumempre5, and EMU68_QEMU_PAYLOAD=divsmemprefffb to exercise DIVU.W and DIVS.W through (A0)+ and -(A0) and confirm the +2 / -2 A0 updates alongside the packed quotient result.
The long-result multiply coverage now also includes EMU68_QEMU_PAYLOAD=mululmempost42, EMU68_QEMU_PAYLOAD=mulslmempost42, EMU68_QEMU_PAYLOAD=mululmempre42, and EMU68_QEMU_PAYLOAD=mulslmempre42 to exercise MULU.L and MULS.L through (A0)+ and -(A0) and confirm the +4 / -4 A0 updates alongside the 32-bit result form.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumemdisp5, EMU68_QEMU_PAYLOAD=divsmemdispfffb, EMU68_QEMU_PAYLOAD=divumemidx5, EMU68_QEMU_PAYLOAD=divsmemidxfffb, EMU68_QEMU_PAYLOAD=mulumemdisp42, EMU68_QEMU_PAYLOAD=mulsmemdisp42, EMU68_QEMU_PAYLOAD=mulumemidx42, EMU68_QEMU_PAYLOAD=mulsmemidx42, EMU68_QEMU_PAYLOAD=mululmemdisp42, EMU68_QEMU_PAYLOAD=mulslmemdisp42, EMU68_QEMU_PAYLOAD=mululmemidx42, and EMU68_QEMU_PAYLOAD=mulslmemidx42 to exercise DIVU.W, DIVS.W, MULU.W, MULS.W, MULU.L, and MULS.L through d16(A0) and brief indexed d8(A0,D1.W) memory-source forms while confirming the resolved target address at A1 = 0x3c100004.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumemidxa1x25, EMU68_QEMU_PAYLOAD=divsmemidxa1x2fffb, EMU68_QEMU_PAYLOAD=divumemlidx4x5, EMU68_QEMU_PAYLOAD=divsmemlidx4xfffb, EMU68_QEMU_PAYLOAD=mulumemidxa1x242, EMU68_QEMU_PAYLOAD=mulsmemidxa1x242, EMU68_QEMU_PAYLOAD=mulumemlidx442, EMU68_QEMU_PAYLOAD=mulsmemlidx442, EMU68_QEMU_PAYLOAD=mululmemidxa1x242, EMU68_QEMU_PAYLOAD=mulslmemidxa1x242, EMU68_QEMU_PAYLOAD=mululmemlidx442, and EMU68_QEMU_PAYLOAD=mulslmemlidx442 to exercise the scaled brief-index mode-6 variants of those same memory-source DIVU.W, DIVS.W, MULU.W, MULS.W, MULU.L, and MULS.L paths through d8(A0,A1.W*2) and d8(A0,D1.L*4), while confirming the resolved target address through A2 = 0x3c100004 on the address-index cases and A1 = 0x3c100004 on the long-index cases.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumemdispovf10000, EMU68_QEMU_PAYLOAD=divsmemdispovf8000, EMU68_QEMU_PAYLOAD=divumemidxa1x2ovf10000, EMU68_QEMU_PAYLOAD=divsmemidxa1x2ovf8000, EMU68_QEMU_PAYLOAD=divumemlidx4ovf10000, and EMU68_QEMU_PAYLOAD=divsmemlidx4ovf8000 to exercise DIVU.W and DIVS.W quotient-overflow handling through d16(A0), d8(A0,A1.W*2), and d8(A0,D1.L*4) memory-source forms while confirming the resolved target address alongside the preserved dividend and D1 = 0xffffffff overflow result.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumemdispztrap31, EMU68_QEMU_PAYLOAD=divsmemdispztrap33, EMU68_QEMU_PAYLOAD=divumemidxa1x2ztrap35, EMU68_QEMU_PAYLOAD=divsmemidxa1x2ztrap37, EMU68_QEMU_PAYLOAD=divumemlidx4ztrap39, and EMU68_QEMU_PAYLOAD=divsmemlidx4ztrap3b to exercise DIVU.W and DIVS.W divide-by-zero vectoring through d16(A0), d8(A0,A1.W*2), and d8(A0,D1.L*4) memory-source forms with in-HUNK handlers returning distinct D0/D1 markers after RTE.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divumempostovf10000, EMU68_QEMU_PAYLOAD=divsmempostovf8000, EMU68_QEMU_PAYLOAD=divumempreovf10000, EMU68_QEMU_PAYLOAD=divsmempreovf8000, EMU68_QEMU_PAYLOAD=divumempostztrap51, EMU68_QEMU_PAYLOAD=divsmempostztrap53, EMU68_QEMU_PAYLOAD=divumempreztrap55, and EMU68_QEMU_PAYLOAD=divsmempreztrap57 to exercise DIVU.W and DIVS.W overflow and divide-by-zero branches through (A0)+ and -(A0) while explicitly confirming the A0 auto-update state that remains after the fault or overflow path returns.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul42, EMU68_QEMU_PAYLOAD=divulz0, EMU68_QEMU_PAYLOAD=divslfffa, EMU68_QEMU_PAYLOAD=divul42r1, EMU68_QEMU_PAYLOAD=divulmem42, and EMU68_QEMU_PAYLOAD=divslmemfffa to exercise ARM32 DIVU.L and DIVS.L through quotient-only, zero-result, signed negative-result, quotient-plus-remainder, and direct-memory forms.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divulmempost42, EMU68_QEMU_PAYLOAD=divslmempostfffa, EMU68_QEMU_PAYLOAD=divulmempre42, and EMU68_QEMU_PAYLOAD=divslmemprefffa to exercise the plain ARM32 DIVU.L and DIVS.L path through (A0)+ and -(A0), confirming the expected +4 and -4 A0 auto-update behavior alongside the quotient result.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divulmemdisp42, EMU68_QEMU_PAYLOAD=divslmemdispfffa, EMU68_QEMU_PAYLOAD=divulmemidxa1x242, EMU68_QEMU_PAYLOAD=divslmemidxa1x2fffa, EMU68_QEMU_PAYLOAD=divulmemlidx442, and EMU68_QEMU_PAYLOAD=divslmemlidx4fffa to exercise those same plain ARM32 DIVU.L and DIVS.L memory-source paths through d16(A0), d8(A0,A1.W*2), and scaled long-index mode-6 forms while confirming the resolved target address through A1 or A2.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64q10000000, EMU68_QEMU_PAYLOAD=divsl64neg3rneg1, EMU68_QEMU_PAYLOAD=divul64memq10000000, and EMU68_QEMU_PAYLOAD=divsl64memneg3rneg1 to exercise the ARM32 64/32 DIVU.L and DIVS.L path in both register and direct-memory forms, confirming 0x00000001:0x00000000 / 16 -> 0x10000000 and signed -10 / 3 -> -3 with remainder -1.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64ovf100000000, EMU68_QEMU_PAYLOAD=divsl64ovf80000000, EMU68_QEMU_PAYLOAD=divul64memovf100000000, and EMU68_QEMU_PAYLOAD=divsl64memovf80000000 to exercise the ARM32 64/32 DIVU.L and DIVS.L overflow path in both register and direct-memory forms, confirming the original D0/D1 dividend pair is preserved while a separate D3 = 0xffffffff marker proves the BVS path was taken.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64ztrap79, EMU68_QEMU_PAYLOAD=divsl64ztrap7b, EMU68_QEMU_PAYLOAD=divul64memztrap7d, and EMU68_QEMU_PAYLOAD=divsl64memztrap7f to exercise ARM32 64/32 DIVU.L and DIVS.L divide-by-zero vectoring through both register and direct-memory forms, confirming the in-HUNK handler returns a distinct D1 marker while the original low dividend remains in D0.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64mempostq10000000, EMU68_QEMU_PAYLOAD=divsl64mempostneg3rneg1, EMU68_QEMU_PAYLOAD=divul64mempreq10000000, and EMU68_QEMU_PAYLOAD=divsl64mempreneg3rneg1 to exercise the ARM32 64/32 DIVU.L and DIVS.L path through (A0)+ and -(A0), confirming the quotient/remainder results alongside the +4 and -4 A0 auto-update behavior.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64mempostovf100000000, EMU68_QEMU_PAYLOAD=divsl64mempostovf80000000, EMU68_QEMU_PAYLOAD=divul64mempreovf100000000, and EMU68_QEMU_PAYLOAD=divsl64mempreovf80000000 to exercise the ARM32 64/32 DIVU.L and DIVS.L overflow path through those same postincrement and predecrement memory-source forms, confirming the preserved high dividend in D1, the separate D3 = 0xffffffff overflow marker, and the final A0 auto-update state.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64mempostztrap49, EMU68_QEMU_PAYLOAD=divsl64mempostztrap4b, EMU68_QEMU_PAYLOAD=divul64mempreztrap4d, and EMU68_QEMU_PAYLOAD=divsl64mempreztrap4f to exercise ARM32 64/32 DIVU.L and DIVS.L divide-by-zero vectoring through (A0)+ and -(A0), confirming the in-HUNK D1 trap markers while D0 stays the original low dividend and A0 still reflects the expected auto-update state after the fault path returns.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64memdispq10000000, EMU68_QEMU_PAYLOAD=divsl64memdispneg3rneg1, EMU68_QEMU_PAYLOAD=divul64memidxa1x2q10000000, EMU68_QEMU_PAYLOAD=divsl64memidxa1x2neg3rneg1, EMU68_QEMU_PAYLOAD=divul64memlidx4q10000000, and EMU68_QEMU_PAYLOAD=divsl64memlidx4neg3rneg1 to exercise the ARM32 64/32 DIVU.L and DIVS.L path through d16(A0), d8(A0,A1.W*2), and scaled long-index memory-source forms while confirming the resolved target address and preserved remainder register.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64memdispovf100000000, EMU68_QEMU_PAYLOAD=divsl64memdispovf80000000, EMU68_QEMU_PAYLOAD=divul64memidxa1x2ovf100000000, EMU68_QEMU_PAYLOAD=divsl64memidxa1x2ovf80000000, EMU68_QEMU_PAYLOAD=divul64memlidx4ovf100000000, and EMU68_QEMU_PAYLOAD=divsl64memlidx4ovf80000000 to exercise the ARM32 64/32 DIVU.L and DIVS.L overflow path through those same non-direct memory forms, confirming the resolved target address and a separate D4 = 0xffffffff overflow marker while the high dividend remains preserved in D1.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divul64memdispztrap81, EMU68_QEMU_PAYLOAD=divsl64memdispztrap83, EMU68_QEMU_PAYLOAD=divul64memidxa1x2ztrap85, EMU68_QEMU_PAYLOAD=divsl64memidxa1x2ztrap87, EMU68_QEMU_PAYLOAD=divul64memlidx4ztrap89, and EMU68_QEMU_PAYLOAD=divsl64memlidx4ztrap8b to exercise ARM32 64/32 DIVU.L and DIVS.L divide-by-zero vectoring through those same displacement and indexed memory-source forms, confirming the in-HUNK handler returns a distinct D1 marker while the original low dividend remains in D0.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divulztrap71, EMU68_QEMU_PAYLOAD=divslztrap73, EMU68_QEMU_PAYLOAD=divulmemztrap75, and EMU68_QEMU_PAYLOAD=divslmemztrap77 to exercise ARM32 DIVU.L and DIVS.L divide-by-zero vectoring through both register and direct-memory forms, with in-HUNK handlers returning distinct D0/D1 markers after RTE.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divulmempostztrap19, EMU68_QEMU_PAYLOAD=divslmempostztrap1b, EMU68_QEMU_PAYLOAD=divulmempreztrap1d, and EMU68_QEMU_PAYLOAD=divslmempreztrap1f to exercise plain ARM32 DIVU.L and DIVS.L divide-by-zero vectoring through (A0)+ and -(A0), confirming the in-HUNK handler markers while A0 still reflects the expected +4 and -4 auto-update state after the fault path returns.
That same MULDIV block now also includes EMU68_QEMU_PAYLOAD=divulmemdispztrap21, EMU68_QEMU_PAYLOAD=divslmemdispztrap23, EMU68_QEMU_PAYLOAD=divulmemidxa1x2ztrap25, EMU68_QEMU_PAYLOAD=divslmemidxa1x2ztrap27, EMU68_QEMU_PAYLOAD=divulmemlidx4ztrap29, and EMU68_QEMU_PAYLOAD=divslmemlidx4ztrap2b to exercise those same plain ARM32 DIVU.L and DIVS.L divide-by-zero paths through d16(A0), d8(A0,A1.W*2), and scaled long-index mode-6 memory forms, confirming that the vectored in-HUNK trap path remains stable beyond direct memory and auto-update modes.
The MOVES coverage also includes EMU68_QEMU_PAYLOAD=movesb_store33, EMU68_QEMU_PAYLOAD=movesb_load7f, EMU68_QEMU_PAYLOAD=movesb_loada80, EMU68_QEMU_PAYLOAD=movesb_posta0, EMU68_QEMU_PAYLOAD=movesb_prea0, EMU68_QEMU_PAYLOAD=movesl_storeef, EMU68_QEMU_PAYLOAD=movesl_load78, EMU68_QEMU_PAYLOAD=movesw_loada34, and EMU68_QEMU_PAYLOAD=movestrap16 to exercise privileged byte, word, and long transfers, address-register sign extension, the same-register (A0)+ and -(A0) auto-update cases, and a user-mode MOVES privilege violation that vectors through an in-HUNK handler, skips the faulting instruction, and returns with D0 = 0x00000010.
The immediate line-0 coverage also includes EMU68_QEMU_PAYLOAD=orib5a, EMU68_QEMU_PAYLOAD=oribmem5a, EMU68_QEMU_PAYLOAD=oribmemdisp5a, EMU68_QEMU_PAYLOAD=oribmemidxa1x25a, EMU68_QEMU_PAYLOAD=oribmempost5a, EMU68_QEMU_PAYLOAD=oribmema7post5a, EMU68_QEMU_PAYLOAD=oribmemabsl5a, EMU68_QEMU_PAYLOAD=andil2468, EMU68_QEMU_PAYLOAD=andiwmem50, EMU68_QEMU_PAYLOAD=andiwmemdisp50, EMU68_QEMU_PAYLOAD=andiwmemidxa1x250, EMU68_QEMU_PAYLOAD=andiwmempre50, EMU68_QEMU_PAYLOAD=andibmema7pre50, EMU68_QEMU_PAYLOAD=andiwmemabsl50, EMU68_QEMU_PAYLOAD=eoribff, EMU68_QEMU_PAYLOAD=eorilmemff, EMU68_QEMU_PAYLOAD=eorilmemdispff, EMU68_QEMU_PAYLOAD=eorilmemlidx4ff, EMU68_QEMU_PAYLOAD=eorilmempostff, EMU68_QEMU_PAYLOAD=eoribmema7postff, EMU68_QEMU_PAYLOAD=eorilmemabslff, EMU68_QEMU_PAYLOAD=addib7f, EMU68_QEMU_PAYLOAD=addiw1234, EMU68_QEMU_PAYLOAD=addil12345678, EMU68_QEMU_PAYLOAD=addibmem1, EMU68_QEMU_PAYLOAD=addiwmem1, EMU68_QEMU_PAYLOAD=addilmem1, EMU68_QEMU_PAYLOAD=addibmemdisp1, EMU68_QEMU_PAYLOAD=addibmemidxa1x21, EMU68_QEMU_PAYLOAD=addibmempre1, EMU68_QEMU_PAYLOAD=addibmema7pre1, EMU68_QEMU_PAYLOAD=addibmemabsl1, EMU68_QEMU_PAYLOAD=subibff, EMU68_QEMU_PAYLOAD=subiwffff, EMU68_QEMU_PAYLOAD=subilffffffff, EMU68_QEMU_PAYLOAD=subibmemff, EMU68_QEMU_PAYLOAD=subiwmemffff, EMU68_QEMU_PAYLOAD=subilmemffffffff, EMU68_QEMU_PAYLOAD=subibmemdisp0, EMU68_QEMU_PAYLOAD=subibmemlidx40, EMU68_QEMU_PAYLOAD=subiwmempost0, EMU68_QEMU_PAYLOAD=subibmema7post0, EMU68_QEMU_PAYLOAD=subiwmemabsl0, EMU68_QEMU_PAYLOAD=cmpibmem2a, EMU68_QEMU_PAYLOAD=cmpiwmem7f, EMU68_QEMU_PAYLOAD=cmpilmem7f, EMU68_QEMU_PAYLOAD=cmpibmemdisp2a, EMU68_QEMU_PAYLOAD=cmpibmemlidx42a, EMU68_QEMU_PAYLOAD=cmpibmempre2a, EMU68_QEMU_PAYLOAD=cmpibmema7pre2a, EMU68_QEMU_PAYLOAD=cmpibmemabsl2a, EMU68_QEMU_PAYLOAD=cmpibpc2a, EMU68_QEMU_PAYLOAD=cmpiwpc7f, EMU68_QEMU_PAYLOAD=cmpilpc7f, EMU68_QEMU_PAYLOAD=cmpibpcidx2a, EMU68_QEMU_PAYLOAD=cmpiwpcidx7f, EMU68_QEMU_PAYLOAD=cmpilpcidx7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1x22a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1x27f, EMU68_QEMU_PAYLOAD=cmpilpcidxa1x27f, EMU68_QEMU_PAYLOAD=cmpibpcidxw2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxw7f, EMU68_QEMU_PAYLOAD=cmpilpcidxw7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1l2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1l7f, EMU68_QEMU_PAYLOAD=cmpilpcidxa1l7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1w2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1w7f, EMU68_QEMU_PAYLOAD=cmpilpcidxa1w7f, EMU68_QEMU_PAYLOAD=cmpibpcidxdl2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxdl7f, EMU68_QEMU_PAYLOAD=cmpilpcidxdl7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1x2neg2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1x2neg7f, EMU68_QEMU_PAYLOAD=cmpilpcidxa1x2neg7f, EMU68_QEMU_PAYLOAD=cmpibpcidxwneg2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxwneg7f, EMU68_QEMU_PAYLOAD=cmpilpcidxwneg7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1wneg2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1wneg7f, and EMU68_QEMU_PAYLOAD=cmpilpcidxa1wneg7f to exercise direct-memory ORI/ANDI/EORI, the previously uncovered ADDI and SUBI register and memory paths across byte, word, and long sizes, CMPI through its memory-source load path, the d16(A0), d8(A0,A1.W*2), d8(A0,D1.L*4), abs.l, d16(PC), and the d8(PC,D1.L*4), d8(PC,A1.W*2), d8(PC,D1.W), d8(PC,A1.L), d8(PC,A1.W), d8(PC,D1.L), negative d8(PC,A1.W*2), negative d8(PC,D1.W), and negative d8(PC,A1.W) immediate EA branches, the (A0)+ and -(A0) auto-update branches, and the byte-sized (A7)+ / -(A7) stack-pointer update-by-2 special case, plus EMU68_QEMU_PAYLOAD=oriccr05, EMU68_QEMU_PAYLOAD=andiccr0a, and EMU68_QEMU_PAYLOAD=eoriccr15 to cover immediate ORI, ANDI, and EORI updates to CCR.
That same PC-index CMPI block now also includes EMU68_QEMU_PAYLOAD=cmpibpcidxdlneg2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxdlneg7f, EMU68_QEMU_PAYLOAD=cmpilpcidxdlneg7f, EMU68_QEMU_PAYLOAD=cmpibpcidxa1lneg2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxa1lneg7f, and EMU68_QEMU_PAYLOAD=cmpilpcidxa1lneg7f to cover the negative unscaled d8(PC,D1.L) and d8(PC,A1.L) long-index branches, where the index contributes -2 instead of a positive offset.
That same PC-index CMPI block now also includes EMU68_QEMU_PAYLOAD=cmpibpcidxdlx4p2a, EMU68_QEMU_PAYLOAD=cmpiwpcidxdlx4p7f, and EMU68_QEMU_PAYLOAD=cmpilpcidxdlx4p7f to cover the positive scaled d8(PC,D1.L*4) branch, complementing the earlier negative long-index scale-4 case with an index contribution of +4.
That same line-0 block now also includes EMU68_QEMU_PAYLOAD=btstimmset, EMU68_QEMU_PAYLOAD=btstdynmod32, EMU68_QEMU_PAYLOAD=btstmemff, EMU68_QEMU_PAYLOAD=btstmemdynff, EMU68_QEMU_PAYLOAD=btstpostff, EMU68_QEMU_PAYLOAD=btstpredynff, EMU68_QEMU_PAYLOAD=btstdispff, EMU68_QEMU_PAYLOAD=btstdispdynff, EMU68_QEMU_PAYLOAD=btstidxa1x2ff, EMU68_QEMU_PAYLOAD=btstidxa1x2dynff, EMU68_QEMU_PAYLOAD=btstidx4ff, EMU68_QEMU_PAYLOAD=btstidx4dynff, EMU68_QEMU_PAYLOAD=bchgreg8, EMU68_QEMU_PAYLOAD=bchgmem08, EMU68_QEMU_PAYLOAD=bchgmemdyn08, EMU68_QEMU_PAYLOAD=bchgpostdyn08, EMU68_QEMU_PAYLOAD=bchgpre08, EMU68_QEMU_PAYLOAD=bchgdisp08, EMU68_QEMU_PAYLOAD=bchgdispdyn08, EMU68_QEMU_PAYLOAD=bchgidxa1x208, EMU68_QEMU_PAYLOAD=bchgidxa1x2dyn08, EMU68_QEMU_PAYLOAD=bchgidx408, EMU68_QEMU_PAYLOAD=bchgidx4dyn08, EMU68_QEMU_PAYLOAD=bclrreg0, EMU68_QEMU_PAYLOAD=bclrmem7f, EMU68_QEMU_PAYLOAD=bclrmemdyn7f, EMU68_QEMU_PAYLOAD=bclrpostdyn7f, EMU68_QEMU_PAYLOAD=bclrpre7f, EMU68_QEMU_PAYLOAD=bclrdisp7f, EMU68_QEMU_PAYLOAD=bclrdispdyn7f, EMU68_QEMU_PAYLOAD=bclridxa1x27f, EMU68_QEMU_PAYLOAD=bclridxa1x2dyn7f, EMU68_QEMU_PAYLOAD=bclridx47f, EMU68_QEMU_PAYLOAD=bclridx4dyn7f, EMU68_QEMU_PAYLOAD=bsetreg8, EMU68_QEMU_PAYLOAD=bsetmem08, EMU68_QEMU_PAYLOAD=bsetmemdyn08, EMU68_QEMU_PAYLOAD=bsetpost08, EMU68_QEMU_PAYLOAD=bsetpre08, EMU68_QEMU_PAYLOAD=bsetpostdyn08, EMU68_QEMU_PAYLOAD=bsetpredyn08, EMU68_QEMU_PAYLOAD=bsetdisp08, EMU68_QEMU_PAYLOAD=bsetdispdyn08, EMU68_QEMU_PAYLOAD=bsetidxa1x208, EMU68_QEMU_PAYLOAD=bsetidxa1x2dyn08, EMU68_QEMU_PAYLOAD=bsetidx408, EMU68_QEMU_PAYLOAD=bsetidx4dyn08, EMU68_QEMU_PAYLOAD=bchgposta708, EMU68_QEMU_PAYLOAD=bclrposta77f, EMU68_QEMU_PAYLOAD=bsetposta708, EMU68_QEMU_PAYLOAD=bchgprea708, EMU68_QEMU_PAYLOAD=bclrprea77f, and EMU68_QEMU_PAYLOAD=bsetprea708 to exercise ARM32 BTST, BCHG, BCLR, and BSET across immediate and register-selected bit numbers, direct register and direct-memory destinations, dynamic-memory bit-number selection, the explicit (A0)+ / -(A0) byte auto-update paths, the d16(A0) displacement branch, the d8(A0,A1.W*2) and d8(A0,D1.L*4) indexed branches, and the separate (A7)+ / -(A7) stack-pointer update-by-2 special cases while confirming both the resulting data byte and the old-bit Z result through follow-up Scc probes.
That same bit-op coverage now also includes EMU68_QEMU_PAYLOAD=btstabslff, EMU68_QEMU_PAYLOAD=btstabsldynff, EMU68_QEMU_PAYLOAD=btstpcff, EMU68_QEMU_PAYLOAD=btstpcdynff, EMU68_QEMU_PAYLOAD=btstpcidxff, EMU68_QEMU_PAYLOAD=btstpcidxdynff, EMU68_QEMU_PAYLOAD=bchgabsl08, EMU68_QEMU_PAYLOAD=bchgabsldyn08, EMU68_QEMU_PAYLOAD=bclrabsl7f, EMU68_QEMU_PAYLOAD=bclrabsldyn7f, EMU68_QEMU_PAYLOAD=bsetabsl08, and EMU68_QEMU_PAYLOAD=bsetabsldyn08 to cover the absolute-long memory branch for BTST, BCHG, BCLR, and BSET, plus the d16(PC) and d8(PC,D1.L*4) PC-relative BTST branches, while still checking both the old-bit Z result and the final memory or inline-data byte.
That same line-0 bit-op block now also includes EMU68_QEMU_PAYLOAD=btstposta7ff, EMU68_QEMU_PAYLOAD=btstposta7dynff, EMU68_QEMU_PAYLOAD=btstprea7ff, EMU68_QEMU_PAYLOAD=btstprea7dynff, EMU68_QEMU_PAYLOAD=bchgposta7dyn08, EMU68_QEMU_PAYLOAD=bclrposta7dyn7f, EMU68_QEMU_PAYLOAD=bsetposta7dyn08, EMU68_QEMU_PAYLOAD=bchgprea7dyn08, EMU68_QEMU_PAYLOAD=bclrprea7dyn7f, and EMU68_QEMU_PAYLOAD=bsetprea7dyn08 to cover the byte-sized (A7)+ and -(A7) stack-pointer update-by-2 branch under both BTST and the register-selected BCHG/BCLR/BSET paths, while still checking the old-bit Z result, the final byte value, and the restored A7 = 0x3f7ff000 state.
The line-4 control-flow coverage also includes EMU68_QEMU_PAYLOAD=bkptret11 and EMU68_QEMU_PAYLOAD=illegalret12 to cover BKPT #0 and ILLEGAL vectoring through an in-HUNK illegal-instruction handler and back to the following instruction, EMU68_QEMU_PAYLOAD=resettrap10 to cover a user-mode RESET privilege violation that vectors through an in-HUNK handler, skips the faulting instruction, and returns with D0 = 0x0000000a, EMU68_QEMU_PAYLOAD=rtdspfb to cover RTD #4 cleaning a stacked longword argument so a framebuffer marker word is exposed at the top of stack, returning D0 = 0x3c1000ff and leaving A7 = 0x3f7ff004 after the marker pop, EMU68_QEMU_PAYLOAD=rtrret05 to cover an RTR control transfer that restores CCR and PC from a manually built stack frame before returning through the original BSR call chain, EMU68_QEMU_PAYLOAD=nopret06 to cover the translated NOP fast path by returning D0 = 0x00000006 after a following ADDQ, EMU68_QEMU_PAYLOAD=jsra04, EMU68_QEMU_PAYLOAD=jsrdisp0b, EMU68_QEMU_PAYLOAD=jsridx17, EMU68_QEMU_PAYLOAD=jsridxa1x265, EMU68_QEMU_PAYLOAD=jsridxa1l75, EMU68_QEMU_PAYLOAD=jsridxw255, EMU68_QEMU_PAYLOAD=jsridxneg45, EMU68_QEMU_PAYLOAD=jsrpc1d, EMU68_QEMU_PAYLOAD=jsrpcidx21, EMU68_QEMU_PAYLOAD=jsrpcidxa1x269, EMU68_QEMU_PAYLOAD=jsrpcidxa1l79, EMU68_QEMU_PAYLOAD=jsrpcidxw259, EMU68_QEMU_PAYLOAD=jsrpcidxneg49, and EMU68_QEMU_PAYLOAD=jsrabsl2d to cover JSR (A0), JSR d16(A0), positive data-register and address-register indexed forms including A1.W*2 and A1.L, word-index *2, and negative long-index JSR d8(A0,Xn), JSR d16(PC), positive data-register and address-register indexed forms including A1.W*2 and A1.L, word-index *2, and negative long-index JSR d8(PC,Xn), and JSR abs.l call/return handoff into separate translated units, EMU68_QEMU_PAYLOAD=jmpa0ret13, EMU68_QEMU_PAYLOAD=jmpdisp0e, EMU68_QEMU_PAYLOAD=jmpidx1a, EMU68_QEMU_PAYLOAD=jmpidxa1x26d, EMU68_QEMU_PAYLOAD=jmpidxa1l7b, EMU68_QEMU_PAYLOAD=jmpidxw25d, EMU68_QEMU_PAYLOAD=jmpidxneg4d, EMU68_QEMU_PAYLOAD=jmppc24, EMU68_QEMU_PAYLOAD=jmppcidx28, EMU68_QEMU_PAYLOAD=jmppcidxa1x271, EMU68_QEMU_PAYLOAD=jmppcidxa1l7d, EMU68_QEMU_PAYLOAD=jmppcidxw261, EMU68_QEMU_PAYLOAD=jmppcidxneg51, and EMU68_QEMU_PAYLOAD=jmpabsl31 to cover direct JMP (A0), JMP d16(A0), positive data-register and address-register indexed forms including A1.W*2 and A1.L, word-index *2, and negative long-index JMP d8(A0,Xn), JMP d16(PC), positive data-register and address-register indexed forms including A1.W*2 and A1.L, word-index *2, and negative long-index JMP d8(PC,Xn), and JMP abs.l handoff into separate translated units, EMU68_QEMU_PAYLOAD=trapv15 to cover a taken TRAPV path that sets overflow in translated code, vectors through an in-HUNK handler, and returns with A7 restored to the supervisor stack top, EMU68_QEMU_PAYLOAD=chkneg14 to cover the negative-input CHK taken-exception path through the same in-HUNK vector setup, EMU68_QEMU_PAYLOAD=chk2low19 to cover the lower-bound CHK2 taken-exception path, and EMU68_QEMU_PAYLOAD=trap3ret07 to cover plain TRAP #3 vectoring through a movec-programmed in-HUNK handler before returning with D0 = 0x00000007, D1 = 0x00000017, and restored A7 = 0x3f7ff000.
The line-4 data-path coverage also includes EMU68_QEMU_PAYLOAD=swap5678, EMU68_QEMU_PAYLOAD=swapz0, EMU68_QEMU_PAYLOAD=swapn80, EMU68_QEMU_PAYLOAD=lea8a0, EMU68_QEMU_PAYLOAD=movemld12, EMU68_QEMU_PAYLOAD=movemlda0, EMU68_QEMU_PAYLOAD=movemst12, EMU68_QEMU_PAYLOAD=movemsta0, EMU68_QEMU_PAYLOAD=movempost12, EMU68_QEMU_PAYLOAD=movempre12, EMU68_QEMU_PAYLOAD=movemprea0, EMU68_QEMU_PAYLOAD=movemposta0, EMU68_QEMU_PAYLOAD=movemwd80, EMU68_QEMU_PAYLOAD=movemwsta0, EMU68_QEMU_PAYLOAD=movemwda0, EMU68_QEMU_PAYLOAD=movemwpost23, EMU68_QEMU_PAYLOAD=movemwposta0, EMU68_QEMU_PAYLOAD=movemwpre23, EMU68_QEMU_PAYLOAD=movemwprea0, EMU68_QEMU_PAYLOAD=chklok9, EMU68_QEMU_PAYLOAD=chkltrap18, EMU68_QEMU_PAYLOAD=movepw5678, EMU68_QEMU_PAYLOAD=movepw_off5678, EMU68_QEMU_PAYLOAD=movepl12345678, EMU68_QEMU_PAYLOAD=movepl_neg12345678, EMU68_QEMU_PAYLOAD=cmp2ok11, EMU68_QEMU_PAYLOAD=cmp2high15, EMU68_QEMU_PAYLOAD=cmp2low16, EMU68_QEMU_PAYLOAD=extwff80, EMU68_QEMU_PAYLOAD=extl8034, EMU68_QEMU_PAYLOAD=extbf80, EMU68_QEMU_PAYLOAD=extf80, EMU68_QEMU_PAYLOAD=linkwsp, EMU68_QEMU_PAYLOAD=linklsp, EMU68_QEMU_PAYLOAD=negx0z, EMU68_QEMU_PAYLOAD=negxbmemffx, and EMU68_QEMU_PAYLOAD=unlka44 to exercise SWAP, including zero and negative flag outcomes, translated LEA with both displacement and register-indirect address calculation, direct MOVEM.L register-list loads from PC-relative data, direct MOVEM.L (A0),A0-A1 base-register loads, direct MOVEM.L register-list stores and reloads through (A0), direct MOVEM.L A0-A1,(A0) base-register stores, postincrement MOVEM.L (A0)+,D1-D2, predecrement MOVEM.L D0-D1,-(A0), predecrement MOVEM.L A0-A1,-(A0) with the base register in the source list and the decremented base value written to memory, postincrement MOVEM.L (A0)+,A0-A1 with the base register in the load list, direct MOVEM.W store/load sign-extension through (A0), direct MOVEM.W A0-A1,(A0) base-register stores, direct MOVEM.W (A0),A0-A1 base-register sign-extending loads, postincrement MOVEM.W (A0)+,D2-D3, postincrement MOVEM.W (A0)+,A0-A1 with the base register in the load list, predecrement MOVEM.W D0-D1,-(A0), predecrement MOVEM.W A0-A1,-(A0) with the base register in the source list and the decremented base value written to memory, both the non-trapping and taken-exception CHK.L paths, MOVEP.W and MOVEP.L round-trips with zero, positive, and negative displacements, CMP2 in-range plus upper- and lower-bound carry-set cases, all three EXT forms, the EXT.W+EXT.L fusion path, both LINK.W and LINK.L paired with UNLK, the sticky-Z register NEGX path, the byte-memory NEGX path with an incoming X carry, and a standalone UNLK A0 frame-pop path that restores A7 = 0x3f7ff000 while returning D0 = 0x11223344.
The line-8/9/B/C arithmetic coverage also includes EMU68_QEMU_PAYLOAD=exgd01, EMU68_QEMU_PAYLOAD=cmpmff, EMU68_QEMU_PAYLOAD=cmpmwff, EMU68_QEMU_PAYLOAD=cmpmlff, EMU68_QEMU_PAYLOAD=cmpmwneg, EMU68_QEMU_PAYLOAD=cmpmlneg, EMU68_QEMU_PAYLOAD=cmpmwcsff, EMU68_QEMU_PAYLOAD=cmpmlcsff, EMU68_QEMU_PAYLOAD=cmpmlvsff, EMU68_QEMU_PAYLOAD=cmpregff, EMU68_QEMU_PAYLOAD=cmpregwff, EMU68_QEMU_PAYLOAD=cmpreglff, EMU68_QEMU_PAYLOAD=cmpcsff, EMU68_QEMU_PAYLOAD=cmpvsff, EMU68_QEMU_PAYLOAD=cmpaeqff, EMU68_QEMU_PAYLOAD=cmpawneg, EMU68_QEMU_PAYLOAD=cmpawmemneg, EMU68_QEMU_PAYLOAD=cmpalcsff, EMU68_QEMU_PAYLOAD=cmpalvsff, EMU68_QEMU_PAYLOAD=cmpalmemff, EMU68_QEMU_PAYLOAD=cmpalmemcsff, EMU68_QEMU_PAYLOAD=cmpalmemvsff, EMU68_QEMU_PAYLOAD=cmpmemff, EMU68_QEMU_PAYLOAD=cmpmemcsff, EMU68_QEMU_PAYLOAD=cmpmemwff, EMU68_QEMU_PAYLOAD=cmpmemlff, EMU68_QEMU_PAYLOAD=cmpmemlvsff, EMU68_QEMU_PAYLOAD=eorregff, EMU68_QEMU_PAYLOAD=eorregwff, EMU68_QEMU_PAYLOAD=eorreglff, EMU68_QEMU_PAYLOAD=eormem00, EMU68_QEMU_PAYLOAD=eormemwff, EMU68_QEMU_PAYLOAD=eormemlff, EMU68_QEMU_PAYLOAD=andreg50, EMU68_QEMU_PAYLOAD=andregw50, EMU68_QEMU_PAYLOAD=andregl50, EMU68_QEMU_PAYLOAD=andmem50, EMU68_QEMU_PAYLOAD=andmemw50, EMU68_QEMU_PAYLOAD=andmeml50, EMU68_QEMU_PAYLOAD=orreg55, EMU68_QEMU_PAYLOAD=orregw55, EMU68_QEMU_PAYLOAD=orregl55, EMU68_QEMU_PAYLOAD=ormem55, EMU68_QEMU_PAYLOAD=ormemw55, EMU68_QEMU_PAYLOAD=ormeml55, EMU68_QEMU_PAYLOAD=divu5, EMU68_QEMU_PAYLOAD=divsfffb, EMU68_QEMU_PAYLOAD=divumem5, EMU68_QEMU_PAYLOAD=divsmemfffb, EMU68_QEMU_PAYLOAD=divuztrap11, EMU68_QEMU_PAYLOAD=divsztrap13, EMU68_QEMU_PAYLOAD=divuovf10000, EMU68_QEMU_PAYLOAD=divsovf8000, EMU68_QEMU_PAYLOAD=divumemovf10000, EMU68_QEMU_PAYLOAD=divsmemovf8000, EMU68_QEMU_PAYLOAD=mulu42, EMU68_QEMU_PAYLOAD=muluz0, EMU68_QEMU_PAYLOAD=mulsm42, EMU68_QEMU_PAYLOAD=mulumem42, EMU68_QEMU_PAYLOAD=mulsmem42, EMU68_QEMU_PAYLOAD=mulul42, EMU68_QEMU_PAYLOAD=mululz0, EMU68_QEMU_PAYLOAD=mulsl42, EMU68_QEMU_PAYLOAD=mululmem42, EMU68_QEMU_PAYLOAD=mulslmem42, EMU68_QEMU_PAYLOAD=addl3, EMU68_QEMU_PAYLOAD=subl3, EMU68_QEMU_PAYLOAD=addlmem3, EMU68_QEMU_PAYLOAD=sublmem3, EMU68_QEMU_PAYLOAD=addlpost3, EMU68_QEMU_PAYLOAD=sublpost3, EMU68_QEMU_PAYLOAD=addlpre3, EMU68_QEMU_PAYLOAD=sublpre3, EMU68_QEMU_PAYLOAD=addaw4, EMU68_QEMU_PAYLOAD=subaw4, EMU68_QEMU_PAYLOAD=addawmemneg, EMU68_QEMU_PAYLOAD=subawmemneg, EMU68_QEMU_PAYLOAD=addalmem4, EMU68_QEMU_PAYLOAD=subalmem4, EMU68_QEMU_PAYLOAD=addbdst1, EMU68_QEMU_PAYLOAD=subbdstfe, EMU68_QEMU_PAYLOAD=addbdstpost1, EMU68_QEMU_PAYLOAD=subbdstpostfe, EMU68_QEMU_PAYLOAD=addbdstpre1, EMU68_QEMU_PAYLOAD=subbdstprefe, EMU68_QEMU_PAYLOAD=addbdsta7post1, EMU68_QEMU_PAYLOAD=subbdsta7postfe, EMU68_QEMU_PAYLOAD=addbdsta7pre1, EMU68_QEMU_PAYLOAD=subbdsta7prefe, EMU68_QEMU_PAYLOAD=addwdst1, EMU68_QEMU_PAYLOAD=subwdst1, EMU68_QEMU_PAYLOAD=addwdstpost1, EMU68_QEMU_PAYLOAD=subwdstpost1, EMU68_QEMU_PAYLOAD=addwdstpre1, EMU68_QEMU_PAYLOAD=subwdstpre1, EMU68_QEMU_PAYLOAD=addldst1, EMU68_QEMU_PAYLOAD=subldst1, EMU68_QEMU_PAYLOAD=addldstpost1, EMU68_QEMU_PAYLOAD=subldstpost1, EMU68_QEMU_PAYLOAD=addldstpre1, EMU68_QEMU_PAYLOAD=subldstpre1, EMU68_QEMU_PAYLOAD=sbcd99x, EMU68_QEMU_PAYLOAD=sbcdpre99x, EMU68_QEMU_PAYLOAD=addx01, EMU68_QEMU_PAYLOAD=addxpre01, EMU68_QEMU_PAYLOAD=subxff, and EMU68_QEMU_PAYLOAD=subxpreff to exercise EXG, CMPM.B/CMPM.W/CMPM.L including equal, negative-result, carry-set, and long overflow-set paths, register and direct-memory CMP.B/CMP.W/CMP.L, including explicit carry-set memory coverage and explicit overflow-set register and long direct-memory cases, address-register CMPA.L, including register carry/overflow and direct-memory equal/carry/overflow paths, a signed register-form CMPA.W source that must sign-extend 0x8000 to match A1 = 0xffff8000, the matching memory-source CMPA.W sign-extension path, register and direct-memory EOR.B/EOR.W/EOR.L, register and direct-memory AND.B/AND.W/AND.L, register and direct-memory OR.B/OR.W/OR.L, register and direct-memory DIVU.W and DIVS.W, their divide-by-zero trap/vector paths through an in-HUNK handler, their quotient-overflow paths with the branch taken and the original destination preserved for both register and direct-memory forms, register and direct-memory MULU.W/MULS.W including zero and negative-result flag cases, register and direct-memory MULU.L/MULS.L in their 32-bit-result forms including zero and negative-result flag cases, plain and memory-source ADD.L/SUB.L through direct, (A0)+, and -(A0) forms, address-register ADDA.W/SUBA.W and ADDA.L/SUBA.L including memory-source sign-extension and longword direct-memory paths, byte, word, and long destination-memory ADD/SUB through direct, (A0)+, and -(A0) forms, including the byte-sized A7 postincrement/predecrement +2/-2 special case, SBCD, ADDX, and SUBX on the ARM32 translator, including the predecrement memory forms that consume an incoming X flag and drive the paired A0/A1 update paths.
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=addbsrca7post1, EMU68_QEMU_PAYLOAD=subbsrca7postff, EMU68_QEMU_PAYLOAD=addbsrca7pre1, and EMU68_QEMU_PAYLOAD=subbsrca7preff to cover the complementary byte-sized (A7)+ and -(A7) source-memory ADD/SUB paths, proving the ARM32 translator takes the stack-pointer +2 / -2 special case on the Ea -> Dn side as well as the already covered destination-memory side.
That same source-memory branch now also includes EMU68_QEMU_PAYLOAD=addbsrc1, EMU68_QEMU_PAYLOAD=subbsrc1, EMU68_QEMU_PAYLOAD=addbsrcpost1, EMU68_QEMU_PAYLOAD=subbsrcpost1, EMU68_QEMU_PAYLOAD=addbsrcpre1, EMU68_QEMU_PAYLOAD=subbsrcpre1, EMU68_QEMU_PAYLOAD=addwsrc1, EMU68_QEMU_PAYLOAD=subwsrc1, EMU68_QEMU_PAYLOAD=addwsrcpost1, EMU68_QEMU_PAYLOAD=subwsrcpost1, EMU68_QEMU_PAYLOAD=addwsrcpre1, and EMU68_QEMU_PAYLOAD=subwsrcpre1 to cover the remaining byte and word non-quick ADD/SUB memory-source forms through direct (A0), (A0)+, and -(A0), including the expected +1 / -1 and +2 / -2 address-register updates.
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=addbsrcdisp1, EMU68_QEMU_PAYLOAD=subbsrcdisp1, EMU68_QEMU_PAYLOAD=addwsrcdisp1, EMU68_QEMU_PAYLOAD=subwsrcdisp1, EMU68_QEMU_PAYLOAD=addlsrcdisp3, EMU68_QEMU_PAYLOAD=sublsrcdisp3, EMU68_QEMU_PAYLOAD=addbdstdisp1, EMU68_QEMU_PAYLOAD=subbdstdisp1, EMU68_QEMU_PAYLOAD=addwdstdisp1, EMU68_QEMU_PAYLOAD=subwdstdisp1, EMU68_QEMU_PAYLOAD=addldstdisp1, EMU68_QEMU_PAYLOAD=subldstdisp1, EMU68_QEMU_PAYLOAD=addawdispneg, EMU68_QEMU_PAYLOAD=subawdispneg, EMU68_QEMU_PAYLOAD=addaldisp4, and EMU68_QEMU_PAYLOAD=subaldisp4 to cover the d16(A0) effective-address branch for non-quick source-memory and destination-memory ADD/SUB, plus ADDA/SUBA word and long memory operands through the same displacement path.
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=addbsrcidx1, EMU68_QEMU_PAYLOAD=subbsrcidx1, EMU68_QEMU_PAYLOAD=addwsrcidx1, EMU68_QEMU_PAYLOAD=subwsrcidx1, EMU68_QEMU_PAYLOAD=addlsrcidx3, EMU68_QEMU_PAYLOAD=sublsrcidx3, EMU68_QEMU_PAYLOAD=addbdstidx1, EMU68_QEMU_PAYLOAD=subbdstidx1, EMU68_QEMU_PAYLOAD=addwdstidx1, EMU68_QEMU_PAYLOAD=subwdstidx1, EMU68_QEMU_PAYLOAD=addldstidx1, EMU68_QEMU_PAYLOAD=subldstidx1, EMU68_QEMU_PAYLOAD=addawidxneg, EMU68_QEMU_PAYLOAD=subawidxneg, EMU68_QEMU_PAYLOAD=addalidx4, and EMU68_QEMU_PAYLOAD=subalidx4 to cover the brief indexed d8(A0,D1.W) effective-address branch for non-quick source-memory and destination-memory ADD/SUB, plus ADDA/SUBA word and long memory operands through the same mode-6 path.
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=addwsrcidxa1, EMU68_QEMU_PAYLOAD=subwsrcidxa1, EMU68_QEMU_PAYLOAD=addwdstidxa1, EMU68_QEMU_PAYLOAD=subwdstidxa1, EMU68_QEMU_PAYLOAD=addawidxa1neg, EMU68_QEMU_PAYLOAD=subawidxa1neg, EMU68_QEMU_PAYLOAD=addlsrcidxl3, EMU68_QEMU_PAYLOAD=sublsrcidxl3, EMU68_QEMU_PAYLOAD=addldstidxl1, EMU68_QEMU_PAYLOAD=subldstidxl1, EMU68_QEMU_PAYLOAD=addalidxl4, and EMU68_QEMU_PAYLOAD=subalidxl4 to cover the remaining brief-index variants for the same non-quick arithmetic family: address-register indexing through d8(A0,A1.W) and true long-indexing through d8(A0,D1.L) with D1 = 0x00010000.
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=addwsrcidxa1x2, EMU68_QEMU_PAYLOAD=subwsrcidxa1x2, EMU68_QEMU_PAYLOAD=addwdstidxa1x2, EMU68_QEMU_PAYLOAD=subwdstidxa1x2, EMU68_QEMU_PAYLOAD=addawidxa1x2neg, EMU68_QEMU_PAYLOAD=subawidxa1x2neg, EMU68_QEMU_PAYLOAD=addlsrcidxl3x4, EMU68_QEMU_PAYLOAD=sublsrcidxl3x4, EMU68_QEMU_PAYLOAD=addldstidx1x4, EMU68_QEMU_PAYLOAD=subldstidx1x4, EMU68_QEMU_PAYLOAD=addalidx4x4, and EMU68_QEMU_PAYLOAD=subalidx4x4 to cover scaled brief-index mode-6 variants for the same non-quick arithmetic family: address-register indexing through d8(A0,A1.W*2) and long-index scaling through d8(A0,D1.L*4).
That same line-B/C memory block now also includes EMU68_QEMU_PAYLOAD=cmpmemwidxa1x2ff, EMU68_QEMU_PAYLOAD=eormemwidxa1x2ff, EMU68_QEMU_PAYLOAD=andmemwidxa1x250, EMU68_QEMU_PAYLOAD=ormemwidxa1x255, EMU68_QEMU_PAYLOAD=cmpmemlidx4ff, EMU68_QEMU_PAYLOAD=eormemlidx4ff, EMU68_QEMU_PAYLOAD=andmemlidx450, and EMU68_QEMU_PAYLOAD=ormemlidx455 to cover scaled brief-index mode-6 addressing in the CMP/EOR/AND/OR memory forms: word operands through d8(A0,A1.W*2) and long operands through d8(A0,D1.L*4).
That same line-B/C memory block now also includes EMU68_QEMU_PAYLOAD=cmpmemidxa1x2ff, EMU68_QEMU_PAYLOAD=eormemidxa1x2ff, EMU68_QEMU_PAYLOAD=andmemidxa1x250, EMU68_QEMU_PAYLOAD=ormemidxa1x255, EMU68_QEMU_PAYLOAD=cmpmemidx4ff, EMU68_QEMU_PAYLOAD=eormemidx4ff, EMU68_QEMU_PAYLOAD=andmemidx450, and EMU68_QEMU_PAYLOAD=ormemidx455 to cover the byte-sized scaled brief-index variants for those same memory forms: address-register indexing through d8(A0,A1.W*2) and long-index scaling through d8(A0,D1.L*4).
That same arithmetic block now also includes EMU68_QEMU_PAYLOAD=cmpmempostff, EMU68_QEMU_PAYLOAD=cmpmempreff, EMU68_QEMU_PAYLOAD=cmpmemwpostff, EMU68_QEMU_PAYLOAD=cmpmemwpreff, EMU68_QEMU_PAYLOAD=cmpmemlpostff, EMU68_QEMU_PAYLOAD=cmpmemlpreff, EMU68_QEMU_PAYLOAD=eormempost00, EMU68_QEMU_PAYLOAD=eormempre00, EMU68_QEMU_PAYLOAD=eormemwpostff, EMU68_QEMU_PAYLOAD=eormemwpreff, EMU68_QEMU_PAYLOAD=eormemlpostff, EMU68_QEMU_PAYLOAD=eormemlpreff, EMU68_QEMU_PAYLOAD=andmempost50, EMU68_QEMU_PAYLOAD=andmempre50, EMU68_QEMU_PAYLOAD=andmemwpost50, EMU68_QEMU_PAYLOAD=andmemwpre50, EMU68_QEMU_PAYLOAD=andmemlpost50, EMU68_QEMU_PAYLOAD=andmemlpre50, EMU68_QEMU_PAYLOAD=ormempost55, EMU68_QEMU_PAYLOAD=ormempre55, EMU68_QEMU_PAYLOAD=ormemwpost55, EMU68_QEMU_PAYLOAD=ormemwpre55, EMU68_QEMU_PAYLOAD=ormemlpost55, and EMU68_QEMU_PAYLOAD=ormemlpre55 to cover the separate byte, word, and long (A0)+ and -(A0) memory-update paths for CMP, EOR, AND, and OR, with the postincrement probes capturing the updated address in A2 before restoring A0 for the in-payload compare.
That same block now includes EMU68_QEMU_PAYLOAD=exgaa01 and EMU68_QEMU_PAYLOAD=exgdafb to cover the remaining EXG address/address and data/address forms.
The Scc matrix also includes EMU68_QEMU_PAYLOAD=snemem00, EMU68_QEMU_PAYLOAD=snepostff, EMU68_QEMU_PAYLOAD=snepost00, EMU68_QEMU_PAYLOAD=snepreff, EMU68_QEMU_PAYLOAD=snepre00, EMU68_QEMU_PAYLOAD=snea7postff, EMU68_QEMU_PAYLOAD=snea7post00, EMU68_QEMU_PAYLOAD=snea7preff, and EMU68_QEMU_PAYLOAD=snea7pre00 to cover direct false stores plus (A0)+, -(A0), (A7)+, and -(A7) memory-destination sne.b paths, including the byte-sized stack-pointer update-by-2 special case.
For example, this verifies that the ARM32 cache-enable bootarg reaches JIT execution and leaves CACR=0x80008000 visible in the context dump:
EMU68_QEMU_BOOTARGS="console=ttyAMA0 skip_reloc enable_cache" \
EMU68_QEMU_EXPECT_EXTRA="CACR=0x80008000" \
scripts/run-qemu-raspi32-smoke.shYou can also probe the ARM32 disassembly path without editing the DTS template:
EMU68_QEMU_BOOTARGS="console=ttyAMA0 skip_reloc disassemble" \
EMU68_QEMU_EXPECT_EXTRA='moveq #$2a, d0' \
scripts/run-qemu-raspi32-smoke.shFor TARGET=raspi builds configured on a host with qemu-system-arm, dtc, and the ARM bare-metal toolchain installed, the same smoke coverage is also registered as ctest tests raspi-arm32-qemu-smoke, raspi-arm32-qemu-loop-smoke, raspi-arm32-qemu-bsr-smoke, raspi-arm32-qemu-cache-smoke, raspi-arm32-qemu-disasm-smoke, raspi-arm32-qemu-stack-smoke, raspi-arm32-qemu-a0mem-smoke, raspi-arm32-qemu-pea-smoke, raspi-arm32-qemu-cmpi-smoke, raspi-arm32-qemu-cmpi-branch-smoke, raspi-arm32-qemu-dbf-smoke, raspi-arm32-qemu-dbne-smoke, raspi-arm32-qemu-dbt-smoke, raspi-arm32-qemu-scc-mem-smoke, raspi-arm32-qemu-scc-true-smoke, raspi-arm32-qemu-scc-false-smoke, raspi-arm32-qemu-scc-reg-sne-smoke, raspi-arm32-qemu-scc-reg-sne-false-smoke, raspi-arm32-qemu-scc-reg-st-smoke, raspi-arm32-qemu-scc-reg-sf-smoke, raspi-arm32-qemu-trapf-word-smoke, raspi-arm32-qemu-trapf-long-smoke, raspi-arm32-qemu-trapf-none-smoke, raspi-arm32-qemu-movec-vbr-smoke, raspi-arm32-qemu-moveusp-smoke, raspi-arm32-qemu-movesr-smoke, raspi-arm32-qemu-movetosr-smoke, raspi-arm32-qemu-moveccr-smoke, raspi-arm32-qemu-nbcd-smoke, raspi-arm32-qemu-nbcd-high-smoke, raspi-arm32-qemu-nbcd-zero-smoke, raspi-arm32-qemu-nbcd-x-smoke, raspi-arm32-qemu-nbcd-predec-smoke, raspi-arm32-qemu-abcd-smoke, raspi-arm32-qemu-abcd-x-smoke, raspi-arm32-qemu-abcd-predec-smoke, raspi-arm32-qemu-pack-smoke, raspi-arm32-qemu-pack-add-smoke, raspi-arm32-qemu-pack-sub-smoke, raspi-arm32-qemu-unpk-smoke, raspi-arm32-qemu-unpk-add-smoke, raspi-arm32-qemu-unpk-sub-smoke, raspi-arm32-qemu-trapt-smoke, raspi-arm32-qemu-trapne-smoke, raspi-arm32-qemu-cas-byte-smoke, raspi-arm32-qemu-cas-byte-fail-smoke, raspi-arm32-qemu-cas-word-smoke, raspi-arm32-qemu-cas-word-fail-smoke, raspi-arm32-qemu-cas-long-smoke, raspi-arm32-qemu-cas-long-fail-smoke, raspi-arm32-qemu-cas2-word-smoke, raspi-arm32-qemu-cas2-word-fail-smoke, raspi-arm32-qemu-cas2-long-smoke, raspi-arm32-qemu-cas2-long-fail-smoke, raspi-arm32-qemu-addq-byte-smoke, raspi-arm32-qemu-subq-byte-smoke, raspi-arm32-qemu-addq-word-smoke, raspi-arm32-qemu-subq-word-smoke, raspi-arm32-qemu-addq-addr-smoke, raspi-arm32-qemu-subq-addr-smoke, raspi-arm32-qemu-addq-postinc-mem-smoke, raspi-arm32-qemu-subq-postinc-mem-smoke, raspi-arm32-qemu-addq-predec-mem-smoke, raspi-arm32-qemu-subq-predec-mem-smoke, raspi-arm32-qemu-addq-a7-postinc-mem-smoke, raspi-arm32-qemu-subq-a7-postinc-mem-smoke, raspi-arm32-qemu-addq-a7-predec-mem-smoke, raspi-arm32-qemu-subq-a7-predec-mem-smoke, raspi-arm32-qemu-addq-long-mem-smoke, raspi-arm32-qemu-subq-long-mem-smoke, raspi-arm32-qemu-addq-long-postinc-mem-smoke, raspi-arm32-qemu-subq-long-postinc-mem-smoke, raspi-arm32-qemu-addq-long-predec-mem-smoke, raspi-arm32-qemu-subq-long-predec-mem-smoke, raspi-arm32-qemu-addq-word-mem-smoke, raspi-arm32-qemu-subq-word-mem-smoke, raspi-arm32-qemu-addq-word-postinc-mem-smoke, raspi-arm32-qemu-subq-word-postinc-mem-smoke, raspi-arm32-qemu-addq-word-predec-mem-smoke, raspi-arm32-qemu-subq-word-predec-mem-smoke, raspi-arm32-qemu-addq-byte-mem-smoke, and raspi-arm32-qemu-subq-byte-mem-smoke.
That matrix also registers raspi-arm32-qemu-moves-store-smoke, raspi-arm32-qemu-moves-load-smoke, raspi-arm32-qemu-moves-load-addr-smoke, raspi-arm32-qemu-moves-postinc-a0-smoke, raspi-arm32-qemu-moves-predec-a0-smoke, raspi-arm32-qemu-moves-long-store-smoke, raspi-arm32-qemu-moves-long-load-smoke, and raspi-arm32-qemu-moves-word-load-addr-smoke.
That matrix also registers raspi-arm32-qemu-exg-smoke, raspi-arm32-qemu-cmpm-smoke, raspi-arm32-qemu-or-reg-smoke, raspi-arm32-qemu-or-mem-smoke, raspi-arm32-qemu-divu-smoke, raspi-arm32-qemu-divs-smoke, raspi-arm32-qemu-divu-mem-smoke, raspi-arm32-qemu-divs-mem-smoke, raspi-arm32-qemu-divu-zero-trap-smoke, raspi-arm32-qemu-divs-zero-trap-smoke, raspi-arm32-qemu-divu-overflow-smoke, raspi-arm32-qemu-divs-overflow-smoke, raspi-arm32-qemu-divu-overflow-mem-smoke, raspi-arm32-qemu-divs-overflow-mem-smoke, raspi-arm32-qemu-mulu-smoke, raspi-arm32-qemu-mulu-zero-smoke, raspi-arm32-qemu-muls-smoke, raspi-arm32-qemu-mulu-mem-smoke, raspi-arm32-qemu-muls-mem-smoke, raspi-arm32-qemu-mulu-long-smoke, raspi-arm32-qemu-mulu-long-zero-smoke, raspi-arm32-qemu-muls-long-smoke, raspi-arm32-qemu-mulu-long-mem-smoke, raspi-arm32-qemu-muls-long-mem-smoke, raspi-arm32-qemu-add-mem-long-smoke, raspi-arm32-qemu-sub-mem-long-smoke, raspi-arm32-qemu-add-mem-long-postinc-smoke, raspi-arm32-qemu-sub-mem-long-postinc-smoke, raspi-arm32-qemu-add-mem-long-predec-smoke, raspi-arm32-qemu-sub-mem-long-predec-smoke, raspi-arm32-qemu-adda-mem-word-smoke, raspi-arm32-qemu-suba-mem-word-smoke, raspi-arm32-qemu-adda-mem-long-smoke, raspi-arm32-qemu-suba-mem-long-smoke, raspi-arm32-qemu-sbcd-smoke, raspi-arm32-qemu-sbcd-predec-smoke, raspi-arm32-qemu-addx-smoke, raspi-arm32-qemu-addx-predec-smoke, raspi-arm32-qemu-subx-smoke, and raspi-arm32-qemu-subx-predec-smoke.
It also registers raspi-arm32-qemu-exg-aa-smoke and raspi-arm32-qemu-exg-da-smoke.
The extended Scc coverage is registered as raspi-arm32-qemu-scc-mem-false-smoke, raspi-arm32-qemu-scc-postinc-smoke, raspi-arm32-qemu-scc-postinc-false-smoke, raspi-arm32-qemu-scc-predec-smoke, raspi-arm32-qemu-scc-predec-false-smoke, raspi-arm32-qemu-scc-a7-postinc-smoke, raspi-arm32-qemu-scc-a7-postinc-false-smoke, raspi-arm32-qemu-scc-a7-predec-smoke, and raspi-arm32-qemu-scc-a7-predec-false-smoke.