GitHub - anhducdinh/Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB: A 32 Bit RISCV Core with APB protocol for data transfer written with SystemVerilog and verilog.

Name		Name	Last commit message	Last commit date
Group 3 G1 VLSI Project Presentation.pptx		Group 3 G1 VLSI Project Presentation.pptx
Group 3 G1 VLSI Project Report.pdf		Group 3 G1 VLSI Project Report.pdf
alu.sv		alu.sv
aludec.sv		aludec.sv
apb.sv		apb.sv
bu.sv		bu.sv
controller.sv		controller.sv
datapath.sv		datapath.sv
extend.sv		extend.sv
flopenr.sv		flopenr.sv
flopr.sv		flopr.sv
instrdec.sv		instrdec.sv
lsu.sv		lsu.sv
mainfsm.sv		mainfsm.sv
mem_wrapper.v		mem_wrapper.v
mux2.sv		mux2.sv
mux3.sv		mux3.sv
prime_test.txt		prime_test.txt
ram.v		ram.v
regfile.sv		regfile.sv
riscv_multi_top.v		riscv_multi_top.v
riscvmulti.sv		riscvmulti.sv
rtl.tcl		rtl.tcl
top_tb.sv		top_tb.sv

About

A 32 Bit RISCV Core with APB protocol for data transfer written with SystemVerilog and verilog.

1 star

0 watching