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Align ADSP SC5XX gpio DTS and driver with Linux #104

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760445b
arm: dts: sc5xx: migrate GPIO to per-port node model
jiez May 14, 2026
32057f8
arm: dts: sc5xx: use ngpios DT property for port pin count
jiez May 20, 2026
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6 changes: 3 additions & 3 deletions arch/arm/dts/sc573-ezlite.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -226,14 +226,14 @@
};

&eth0 {
snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('A', 5) GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpa 5 GPIO_ACTIVE_LOW>;
};

&gpio0 {
&gpa {
emac0_phy_pwdn {
gpio-hog;
output-high;
gpios = <ADI_ADSP_PIN('A', 4) GPIO_ACTIVE_HIGH>;
gpios = <4 GPIO_ACTIVE_HIGH>;
};
};

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15 changes: 13 additions & 2 deletions arch/arm/dts/sc57x.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -94,8 +94,19 @@
adi,npins = <92>;
};

&gpio0 {
adi,ngpios = <92>;
/ {
scb {
gpf: gpio@31004280 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004280 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "F";
ngpios = <12>;
status = "okay";
bootph-pre-ram;
};
};
};

&clk {
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6 changes: 3 additions & 3 deletions arch/arm/dts/sc584-ezkit.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -233,13 +233,13 @@
};

&eth0 {
snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('B', 14) GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpb 14 GPIO_ACTIVE_LOW>;
};

&gpio0 {
&gpc {
emac0_phy_pwdn {
gpio-hog;
output-high;
gpios = <ADI_ADSP_PIN('C', 15) GPIO_ACTIVE_HIGH>;
gpios = <15 GPIO_ACTIVE_HIGH>;
};
};
6 changes: 3 additions & 3 deletions arch/arm/dts/sc589-ezkit.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -197,14 +197,14 @@
};

&eth0 {
snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('B', 14) GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpb 14 GPIO_ACTIVE_LOW>;
};

&gpio0 {
&gpc {
emac0_phy_pwdn {
gpio-hog;
output-high;
gpios = <ADI_ADSP_PIN('C', 15) GPIO_ACTIVE_HIGH>;
gpios = <15 GPIO_ACTIVE_HIGH>;
};
};

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6 changes: 3 additions & 3 deletions arch/arm/dts/sc589-mini.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,14 @@
};

&eth0 {
snps,reset-gpio = <&gpio0 ADI_ADSP_PIN('B', 7) GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpb 7 GPIO_ACTIVE_LOW>;
};

&gpio0 {
&gpf {
emac0_phy_pwdn {
gpio-hog;
output-high;
gpios = <ADI_ADSP_PIN('F', 6) GPIO_ACTIVE_HIGH>;
gpios = <6 GPIO_ACTIVE_HIGH>;
};
};

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26 changes: 24 additions & 2 deletions arch/arm/dts/sc58x.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -128,8 +128,30 @@
adi,npins = <102>;
};

&gpio0 {
adi,ngpios = <102>;
/ {
scb {
gpf: gpio@31004280 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004280 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "F";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpg: gpio@31004300 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004300 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "G";
ngpios = <6>;
status = "okay";
bootph-pre-ram;
};
};
};

&clk {
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14 changes: 8 additions & 6 deletions arch/arm/dts/sc598-htol.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
clock-names = "sclk0";
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rts-gpios = <&gpio0 ADI_ADSP_PIN('D', 1) GPIO_ACTIVE_HIGH>;
rts-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
Expand All @@ -34,33 +34,35 @@
};
};

&gpio0 {
&gpb {
uart0-en {
gpio-hog;
gpios = <ADI_ADSP_PIN('B', 13) GPIO_ACTIVE_LOW>;
gpios = <13 GPIO_ACTIVE_LOW>;
output-high;
line-name = "uart0-en";
bootph-pre-ram;
};

uart0-flow-en {
gpio-hog;
gpios = <ADI_ADSP_PIN('B', 14) GPIO_ACTIVE_LOW>;
gpios = <14 GPIO_ACTIVE_LOW>;
output-low;
line-name = "uart0-flow-en";
bootph-pre-ram;
};
};

&gpe {
led1 {
gpio-hog;
gpios = <ADI_ADSP_PIN('E', 15) GPIO_ACTIVE_LOW>;
gpios = <15 GPIO_ACTIVE_LOW>;
output-high;
line-name = "led1";
};

led2 {
gpio-hog;
gpios = <ADI_ADSP_PIN('E', 10) GPIO_ACTIVE_LOW>;
gpios = <10 GPIO_ACTIVE_LOW>;
output-high;
line-name = "led2";
};
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76 changes: 61 additions & 15 deletions arch/arm/dts/sc59x.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,9 @@
spi0 = "/ospi";
};

soc {
scb {
rcu: rcu@0x3108C000 {
compatible = "adi,reset-controller";
compatible = "adi,reset-controller", "syscon";
reg = <0x3108C000 0x1000>;
adi,sharc-min = <1>;
adi,sharc-max = <2>;
Expand Down Expand Up @@ -69,9 +69,7 @@
usb0_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reset = <&gpio0 ADI_ADSP_PIN('G', 11) GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb0_default>;
reset-gpios = <&gpg 11 GPIO_ACTIVE_LOW>;
status = "disabled";
};

Expand All @@ -90,29 +88,29 @@
i2c3: i2c3@31001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi-i2c";
compatible = "adi,twi";
reg = <0x31001000 0x100>;
clock-names = "i2c";
clock-names = "sclk0";
status = "disabled";
bootph-pre-ram;
};

i2c4: i2c4@31001100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi-i2c";
compatible = "adi,twi";
reg = <0x31001100 0x100>;
clock-names = "i2c";
clock-names = "sclk0";
status = "disabled";
bootph-pre-ram;
};

i2c5: i2c5@31001200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi-i2c";
compatible = "adi,twi";
reg = <0x31001200 0x100>;
clock-names = "i2c";
clock-names = "sclk0";
status = "disabled";
bootph-pre-ram;
};
Expand Down Expand Up @@ -186,20 +184,68 @@
};
};

&gpio0 {
adi,ngpios = <135>;
/ {
scb {
gpf: gpio@31004280 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004280 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "F";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpg: gpio@31004300 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004300 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "G";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gph: gpio@31004380 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004380 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "H";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpi: gpio@31004400 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004400 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "I";
ngpios = <7>;
status = "okay";
bootph-pre-ram;
};
};
};

&gpd {
pushbutton0 {
gpio-hog;
input;
gpios = <ADI_ADSP_PIN('D', 0) GPIO_ACTIVE_HIGH>;
gpios = <0 GPIO_ACTIVE_HIGH>;
bootph-pre-ram;
};
};

&gph {
pushbutton1 {
gpio-hog;
input;
gpios = <ADI_ADSP_PIN('H', 0) GPIO_ACTIVE_HIGH>;
gpios = <0 GPIO_ACTIVE_HIGH>;
bootph-pre-ram;
};
};
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52 changes: 49 additions & 3 deletions arch/arm/dts/sc5xx.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -71,11 +71,57 @@
bootph-pre-ram;
};

gpio0: gpio@0x31004000 {
compatible = "adi,adsp-gpio";
reg = <0x31004000 0x500>;
gpa: gpio@31004000 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004000 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "A";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpb: gpio@31004080 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004080 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "B";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpc: gpio@31004100 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004100 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "C";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpd: gpio@31004180 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004180 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "D";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};

gpe: gpio@31004200 {
compatible = "adi,adsp-port-gpio";
reg = <0x31004200 0x80>;
gpio-controller;
#gpio-cells = <2>;
adi,bank-name = "E";
ngpios = <16>;
status = "okay";
bootph-pre-ram;
};
Expand Down
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