Upgrade TransceiverToolbox to 2026-r1 release, Vivado 2025.1, and add deployed loopback scaling tests

[tfcollins]

Description

This PR upgrades TransceiverToolbox to the 2026-r1 release of the ADI HDL repository and AMD/Xilinx Vivado 2025.1 tools, and adds hardware loopback validation with dynamic runtime channel scaling.

Summary of Changes

1. HDL Repository & Vivado 2025.1 Upgrade:

   • Updated +adi/Version.m to HDL = 'hdl_2026_r1' and Vivado = '2025.1'.
   • Fixed gtwiz_parser.pl git-tracked check in hdl/vendor/AnalogDevices/vivado/projects/scripts/gtwiz_parser.pl so make succeeds during non-git / temporary directory BSP creation.
   • Updated board reference design plugins (plugin_rd.m) and ports.json.

2. Deployed Hardware Loopback & Runtime Channel Scaling Test:

   • Added DeployedLoopbackTests.m inheriting from HardwareTests.
   • Configured AXI4-Lite register mapping (0x108 / regWrite1) for dynamic channel scaling.
   • Verified transceiver digital loopback and dynamic runtime channel scaling against target hardware (AD9371+ZC706).
   • Integrated DeployedLoopbackTests into runHWTests.m.

Testing

• Verified AD9371+ZC706 reference design builds cleanly with Vivado 2025.1 and generates valid system_top.bit and system_top.xsa.
• Verified BOOT.BIN packaging using AMD/Xilinx Vivado 2025.1 bootgen v2025.1.
• Flashed and booted AD9371+ZC706 target hardware via XSDB JTAG (BOOT_JTAG_SUCCESS).
• Validated DeployedLoopbackTests in MATLAB R2025b.