Public technical dossier for a five-stage pipelined RISC-V processor project, implementing the RV32I base instruction set with selected RV32M multiplication instructions, cache integration, hazard handling, and branch-prediction extensions.
Source code is not published here because the original implementation was produced for university coursework and may be subject to academic integrity restrictions. This repository documents the architecture, feature coverage, verification approach, and engineering evidence without exposing restricted RTL or test source.
This project implemented a 32-bit RISC-V processor in SystemVerilog. The design evolved from a single-cycle processor into a five-stage pipelined processor with forwarding, stalling, flushing, cache integration, full RV32I support, and selected M-extension multiplication instructions.
The final design included:
- a five-stage pipeline: Fetch, Decode, Execute, Memory, Writeback,
- hazard detection and forwarding,
- branch and jump handling,
- a two-way set-associative write-back cache,
- complete RV32I base instruction support,
- selected RV32M multiplication instructions,
- a dynamic branch predictor extension,
- Verilator/GoogleTest-style component and system verification,
- an F1-style start-lights assembly demonstration.
| Area | Result |
|---|---|
| ISA | RV32I base instruction set |
| Extension | RV32M multiplication subset: MUL, MULH, MULHSU, MULHU |
| Microarchitecture | Five-stage pipelined processor |
| Hazard handling | Forwarding, load-use stalls, control-hazard flushing, cache stalls |
| Memory extension | Two-way set-associative write-back cache |
| Branch extension | 2-bit dynamic branch predictor with PHT/BTB-style behaviour |
| Verification | Component-level and full-system simulation using assembly test programs |
| Demo | F1-style start-lights program in RISC-V assembly |
flowchart TD
A["Fetch"] --> B["Decode"]
B --> C["Execute"]
C --> D["Memory"]
D --> E["Writeback"]
The full RV32I base instruction set required updates across the ALU, control unit, branch unit, immediate generation, pipeline registers, memory path, and writeback routing.
The processor included a two-way set-associative write-back cache integrated into the pipelined memory stage. Cache misses stall the pipeline while the cache state machine completes writeback/fetch/update behaviour.
The branch prediction extension used a 2-bit saturating counter style predictor. Predictions are made during fetch, while actual branch resolution occurs later and trains the predictor.
- SystemVerilog
- RISC-V RV32I/RV32M concepts
- Five-stage CPU pipeline design
- Hazard detection and forwarding
- Cache design
- Branch prediction
- Verilator
- C++ / GoogleTest-style testbenches
- RISC-V assembly
The implementation source is intentionally private. I can discuss the datapath, hazard logic, control changes, cache integration, multiplication extension, branch-prediction design, and verification strategy in interviews. Where permitted, I can provide supervised evidence of code ownership without publishing restricted coursework material.