Logic Design

NTU 2016 Fall Semester

Class: 交換電路與邏輯設計 Switching Circuit and Logic Design

Professor: 楊家驤　Chia-Hsiang Yang

Name		Name	Last commit message	Last commit date
Extension		Extension
Final link		Final link
Final vivado/Final link_new		Final vivado/Final link_new
LAB10 link_WORK		LAB10 link_WORK
LAB11 link_work		LAB11 link_work
LAB12 link_work		LAB12 link_work
LAB7 NEW		LAB7 NEW
LAB7 link		LAB7 link
LAB8_hw		LAB8_hw
LAB9_HW		LAB9_HW
lab_hw3		lab_hw3
lab_hw4		lab_hw4
lab_hw5		lab_hw5
lab_hw6		lab_hw6
LD 2016 Verilog.pdf		LD 2016 Verilog.pdf
LD2016-12.ppt		LD2016-12.ppt
LD2016_12.zip		LD2016_12.zip
Logic Design Project Baseline.mp4		Logic Design Project Baseline.mp4
README.md		README.md

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