Xezim — Extensible SystemVerilog Simulator. Zero lock-in.
An open-source SystemVerilog simulator, written in Rust.
RTL, gate-level and UVM simulation in one command, from source to results.
User guide · Command line · UVM · DPI & VPI · Release notes · Contributing
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From source to results in one command
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RTL to gate level
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Verification
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Debug and integration
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Fast to iterate
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Open
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The feature list has the details.
Xezim reads Verilog and SystemVerilog source files and simulates them. It
preprocesses and parses the sources, elaborates the design hierarchy, compiles
processes and continuous assignments into bytecode, and runs them on an
event-driven kernel that follows the IEEE 1800 scheduling semantics. Most
logic runs on fast two-state executors, which fall back to full four-state
evaluation wherever x and z values appear.
Everything happens in one invocation, so a design goes from source to results without a separate build step, and a test suite made of many short runs gets its answers quickly. The same command line works for an RTL unit test, a gate-level netlist with SDF timing, or a full UVM environment.
git clone https://github.com/aionhw/xezim.git
cd xezim
cargo build --release # or ./scripts/build-pgo.sh for a profile-guided build// counter.sv
module counter_tb;
logic clk = 0, rst = 1;
logic [3:0] count;
always #5 clk = ~clk;
always_ff @(posedge clk) count <= rst ? '0 : count + 1;
initial begin
#12 rst = 0;
repeat (3) @(posedge clk) $display("t=%0t count=%0d", $time, count);
$finish;
end
endmodule$ ./target/release/xezim counter.sv
t=15 count=0
t=25 count=1
t=35 count=2
Simulation finished at time 35 ($finish called)
A UVM testbench needs only the UVM sources on the command line:
xezim -s top -I $UVM/src $UVM/src/uvm_pkg.sv <design and testbench files> \
+UVM_TESTNAME=my_testSee the user guide and the UVM guide for more.
Whole-run wall-clock time on one machine (Intel Core i7-9800X, six logical CPUs, Linux). The Xezim 0.11.3 figures were measured with a plain release build and cold caches. Reference figures are from earlier verified runs on the same machine in optimized mode, without debug visibility. Both simulators produce the same results on every row.
| Workload | Xezim | Reference simulator |
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| XuanTie C906 SoC, CoreMark ×1 (295,294 cycles) | 82 s, 0.62 GiB peak | 82 s, 44 s of it simulating |
| XuanTie C910 dual-core SoC, memcpy ×200, cold start | 121 s, about 12 s of it compiling | 136 s, 97 s of it simulating |
| AXI4 AVIP, UVM base test | 7.8 s | 97 s, 51 s of it simulating |
AXI4 is the median of five runs; each SoC figure is one run. Host load affects elapsed time, so these figures describe the measured workloads rather than a controlled comparison. Compilation and elaboration account for only a small part of these Xezim runs, making startup cost useful to consider separately from simulation time.
To get the most out of a build, measure a profile-guided build trained on your own workload and keep the warm design cache on. Native compilation pays on designs with few, very hot blocks, so measure it on yours.
- sv-tests: Xezim 0.11.0 passes 4,722 of 4,770 tests (99.0%) of the sv-tests suite.
- UVM: the mbits-mirafra AVIP base tests for AXI4, APB, I3C, SPI and AXI4-Lite print the same UVM messages as a commercial reference simulator, and 32 of 35 UVM 1800.2-2017 example testbenches pass.
- Regression suite: 6,610 default tests and two JIT smoke tests run in CI. Many are differential tests whose expected values were measured on a commercial reference simulator; see CONTRIBUTING.md.
| Guide | Contents |
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| Supported features | Language, UVM, coverage, debug and integration features in detail |
| User guide | Running simulations, waveforms, checkpoints, design cache, native compilation, timescales, sources written for other simulators |
| Command-line reference | Every option and environment variable, and the spellings of other simulators that Xezim accepts |
| UVM guide | Running UVM testbenches, supported features, UVM's DPI-C library |
| DPI and VPI guide | Loading C and C++ libraries, the VPI surface |
| Coverage guide | Functional, assertion and code coverage, xezim_cov.json |
| UPF guide | IEEE 1801 power intent |
| Debugging guide | Tracing, diagnosing hangs, comparing against another simulator |
| Building from source | Requirements, profile-guided builds, working on xezim-core |
| Release notes | Changes per release, verified workloads, compliance results |
Questions, bug reports and feature requests go to GitHub issues. A small self-checking testcase gets a bug fixed fastest; see CONTRIBUTING.md for what to include. Pull requests are welcome.
Xezim explores whether modern tools and AI assistance can sharply reduce the cost of building core EDA infrastructure such as a simulator: work that has traditionally taken large teams many years. It was built incrementally, from simple combinational logic up to SoCs and UVM environments, with every step verified against the language standard and against a commercial reference simulator. Longer term, the project looks at cloud-scale and distributed multi-CPU simulation.
The project was previously developed under the name sisSIM.
Thank you to everyone who contributes code, tests and bug reports to Xezim and xezim-core.
See CONTRIBUTORS.md for what each person contributed, and CONTRIBUTING.md to get involved.
- The Icarus Verilog project, for its public test suite
- The sv-tests project
- The Rust community and the open-source EDA projects Xezim builds on
Xezim is free software, licensed under the Apache License 2.0.