Cache Controller

Features

• L1 Cache: Direct-mapped
• L2 Cache: 4-way set-associative
• Replacement Policy: LRU (Least Recently Used)
• Write Policy: Write-back with no-write-allocate

Project Structure

Folder	Purpose
Simulation	Full simulation with comprehensive comments and real-world memory sizes
FPGA	Synthesizable code with reduced memory sizes for FPGA deployment
Waveforms	Simulation waveform screenshots

Quick Start

1. Open project in Xilinx Vivado
2. Load the .xpr file from Simulation or FPGA folder
3. Run simulation or synthesize

Results

Simulation Waveforms