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abdelrahman-fouda/README.md

Abdelrahman Fouda

M.Sc. Electronic Engineering candidate at the University of Bologna working across neuromorphic AI, robotics, embedded systems, and digital hardware.

I enjoy turning research ideas into measurable engineering systems: spiking neural-network controllers in GPU-parallel simulation, TinyML models on microcontrollers, RISC-V accelerators, and transistor-level CMOS designs.

Selected work

Integrated snnTorch policies with SKRL PPO for quadcopter control in NVIDIA Isaac Lab. The tuned SNN reached +14% peak reward over the matched MLP baseline, while a sparsity-aware variant used about 88% fewer spikes at comparable reward. Reward shaping reduced control jerk by 70%.

Python · PyTorch · snnTorch · SKRL · Isaac Lab · Reinforcement Learning

Built an obstacle-avoidance workflow around a Raspberry Pi Pico, range sensing, Q-learning-assisted data collection, and quantized TensorFlow Lite inference. The deployed model achieved 83.9% on-device accuracy.

Python · TensorFlow Lite · TinyML · Raspberry Pi Pico · Embedded AI

Designed a 384-cell SRAM macro in Cadence Virtuoso, including the bit cell, row/column decoders, write driver, and latch-type sense amplifier. Verified read/write behavior, static noise margin, delay, power, and physical layout.

Cadence Virtuoso · CMOS · Memory Design · Circuit Simulation · Layout

Designed and simulated a two-stage operational amplifier in 65 nm CMOS using the gm/Id methodology, transistor-level biasing, compensation, and layout-aware analysis.

Analog IC Design · Cadence Virtuoso · gm/Id · 65 nm CMOS

Current focus

  • Neuromorphic computing and energy-efficient AI
  • Reinforcement learning for cyber-physical systems
  • Embedded ML and edge deployment
  • RISC-V microarchitecture and hardware acceleration
  • Digital/analog IC design and verification

Education

  • M.Sc. Electronic Engineering (LM-29) — University of Bologna, 2025–present
  • B.Sc. Nanotechnology and Nanoelectronics Engineering, VLSI concentration — Zewail City, 2020–2025

Core tools

  • Programming: Python, C, C++, MATLAB, Assembly
  • Hardware: Verilog, SystemVerilog, RISC-V, FPGA/ASIC flows
  • AI/Robotics: PyTorch, TensorFlow Lite, reinforcement learning, Isaac Lab
  • EDA & simulation: Cadence Virtuoso, ModelSim, Silvaco TCAD, COMSOL, Lumerical, Ansys, Proteus

Contact

Pinned Loading

  1. Photonic-Crystal-Fiber-Simulation Photonic-Crystal-Fiber-Simulation Public

    Simulation study of a hybrid plasmonic liquid-crystal photonic fiber coupler for 1.3/1.55 um MUX-DEMUX operation.

    1

  2. Two-Stage-CMOS-operational-amplifier Two-Stage-CMOS-operational-amplifier Public

    Two-stage 65 nm CMOS operational amplifier designed in Cadence Virtuoso using the gm/Id methodology.

    1

  3. -Internet-Phone-Filter-Splitter -Internet-Phone-Filter-Splitter Public

    Passive ADSL voice/data splitter designed, simulated, prototyped, and routed as a manufacturing-ready PCB.

  4. Design-of-a-32-12-bits-6T-SRAM-Using-65nm-Cadence- Design-of-a-32-12-bits-6T-SRAM-Using-65nm-Cadence- Public

    Transistor-level design and physical layout of a 32 x 12-bit 6T SRAM macro in 65 nm CMOS.

  5. SNN-RL-IsaacLab SNN-RL-IsaacLab Public

    Spiking neural-network policies for quadcopter reinforcement learning in NVIDIA Isaac Lab, built with snnTorch and SKRL.

    Python

  6. TinyMLObstacleAvoidanceWheeledRobot TinyMLObstacleAvoidanceWheeledRobot Public

    TinyML obstacle-avoidance robot with Q-learning-assisted simulation and quantized TensorFlow Lite inference.

    Python