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Group 22: RISC-V Processor

Group 22 Team Statement

Our group has succesfully implemented and verified the following for our RV32I processor (note that the majority of this testing took place using gtkwave simulator)

Other Implementations
Single cycle simple cpu

The following blocks and tasks were distributid amongs the group as such:
Note the key : M - Major contribution p - partial contribution

Block / feature Denzil Erza-Essien 02593040 Morris Griffin 02616740 Apshara Amiruzzaman 02383793 Dzuldiniy Hussain bin Dzulkeflee 02574233
Bpredictor.sv M
Branch_taken.sv M M
alu.sv p M
control_unit.sv M M
data_mem_cache.sv M p
hazard_unit.sv M p
instructionmemory.sv M
pc.sv p M
registerfile.sv M
signextend.sv p M
top.sv M
Pipelined design M p
Full instruction implementation M M
Verification M M

Testbench and Working Evidence

Simulating tests

The following commands (and descriptions) run the following script files to allow for testing:

Command Description
source start.sh Runs the file program.S in gtkwave
source run_f1.fsm Runs the f1 fsm in gtkwave

Working Evidence

When simulating, the five .mem files were used to check for correct implementation. This can be seen in the following screenshots:


Test 1 - program.S

Test 2 - Data Hazards + ALU Implementation

Test 3 - Forwarding + Memory Management

Test 4 - Multiple consecutive stores and loads

Test 5 - bne instruction implementation

After this, a simple F1 program was also tested to ensure everything worked as expected:


F1 Program - gtkwave simulation:

Contribution notes

The project was completed using git commands throughout. Specific implementations were made in branches and then merged into the main. This also allowed us to have different variants of the processor as required.

Although the commits and table do roughly represent the contribution of each team member, the following must also be noted:

  • In some implementations, mainly those in which partial involvement is present, people may have been working together (whilst one person pushes into the repo), hence showing commit history for only one person.
  • Although some of the blocks were trivial in theory, when implementing to the top file, there was a multitude of debugs all of which took hours to resolve, hence masking the time and contribution of members.
  • Even with some of the more trivial implementations, given the further extensions, these basic blocks had to be extended to ensure complete design was achieved. This required time which may not be shown and collaboration between group members for all the blocks present.

We believe that the personal statements combined with the commit history and contribution table accurately represent the contribution of each member in the team.

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Lab 4 2025

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