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  • German University in Cairo (GUC)
  • Cairo, Egypt

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ZiadAbaid/README.md

Ziad Ahmed Abaid Elshazly

B.Sc. in Electronics Engineering Candidate — German University in Cairo (GUC)
Cumulative GPA: 1.27 (German Scale: Best 0.7, Worst 5.0) · Full-Tuition Academic Scholarship (Top 150 Nationwide)
Co-Head, Hardware for AI Committee — IEEE GUC Student Branch

📧 ziad.abaid@student.guc.edu.eg · 🔗 LinkedIn · 📍 Cairo, Egypt

Research & Engineering Focus

My work bridges Digital Hardware Acceleration for AI, Hardware-Software Co-Design, Silicon Photonics, and Mixed-Signal / RF Engineering:

  • FPGA & SoC Neural Network Accelerators: Architecting parameterized pure-VHDL RTL engines for Convolutional Neural Networks on Xilinx Zynq-7000 (XC7Z020) and Artix-7 (XC7A100T) platforms—including multiplierless CFGLUT5 lookup-network + Dadda tree datapaths (0 DSP48 slices), Q8.8 fixed-point streaming pipelines with custom 144-bit single-cycle BRAM ROMs, and PetaLinux 64-bit AXI-DMA / high-speed SPI co-design.
  • Silicon Photonics & Optical Interconnects: Electromagnetic modeling and S-parameter extraction of serially coupled SOI microring resonators in Ansys Lumerical (FDTD, MODE, DGTD, INTERCONNECT) and computer-vision-driven motorized fiber-to-chip alignment (YOLOv8, $0.6^\circ$ angular accuracy) at the GUC Micro Optics Laboratory.
  • Embedded DSP, RF & Semiconductor Physics: Edge biomedical IIR filtering on ESP32/Raspberry Pi 5 IoMT networks, full-wave 3D EM microstrip filter synthesis in CST Microwave Studio, quantum-well laser diode TCAD optimization in Silvaco Atlas, and discrete analog circuit design.

Featured Repositories & Hardware Projects

Project / Repository Target Platform & Tools Key Quantitative Results
FPGA-CNN-Inference-Accelerator
5-Layer Q8.8 Fixed-Point Streaming CNN Accelerator 		Artix-7 FPGA (Nexys 4) & Raspberry Pi 5
Pure VHDL RTL · AXI-Stream · 8 MHz 16-bit SPI · Python 		• 100/100 (100%) bit-exact parity vs. Python Q8.8 golden model
• ~15× fewer clock cycles (35k @ 100 MHz vs. 528k on Pi 5 TFLite FP32)
• 0.002 ms (~200 cycles) post-SPI pipeline flush · 0 WNS violations
Multiplierless Zynq-7000 CNN SoC Accelerator
(IEEE SSCS Design Competition — Private Repo) 		Zynq-7000 SoC (ZedBoard XC7Z020)
Pure VHDL RTL · CFGLUT5 · Dadda Trees · PetaLinux AXI-DMA 		• 0 DSP48 slices & 0 core BRAMs across 5 hardware profiles (15–65 mW @ 125 MHz)
• 577 bit-exact frames verified on silicon (0.123–0.145 ms/frame DMA latency)
• 70.08% CIFAR-10 accuracy with hybrid C++ ARM classifier & live Web GUI
Silicon-Photonics-Ring-Resonators
Coupled Microring Resonator PIC Modeling 		Ansys Lumerical (FDTD, MODE, INTERCONNECT) · Python / YOLO • Multi-port S-matrix extraction (bus-ring, ring-ring) & C-band FSR/$Q$-factor analysis
• Automated motorized stage fiber alignment ($0.6^\circ$ angular precision)
Smart-Medical-IoMT-System
Distributed IoMT Edge DSP & Telemetry Gateway 		ESP32 (C++ Dual-I2C/OneWire) & Raspberry Pi 5 (Python, TLS MQTT, SQLite) • On-chip $0.8\text{–}3.5\text{ Hz}$ IIR bandpass PPG filter + EMA smoothing (validated vs. Huawei Watch GT 2)
• 25 FPS real-time ECG/$\text{SpO}_2$ GUI & $<2\text{ s}$ autonomous hardware/Telegram alarm loop
RF-Analog-Semiconductor-Engineering
RF Microstrip LPF, QW Laser TCAD & Class-AB Amp 		CST Microwave Studio · Silvaco Atlas · KiCad & Proteus • 5.0 GHz 7th-Order Chebyshev LPF: Kuroda transforms & 3D EM optimization ($S_{11} < -15\text{ dB}$)
• InGaP QW/BH Laser TCAD: $20\times$ gain boost & 40% $I_{\text{th}}$ reduction ($5\text{ mA} \to 3\text{ mA}$)
• 4-Stage Class-AB BJT Amplifier: $-17.0\text{ V/V}$ loaded gain into $8,\Omega$ speaker
Lead-Lag-Control-System-Optimization
Closed-Loop Lead-Lag Synthesis & Simplex Optimization 		MATLAB & Simulink (Control System Toolbox, fminsearch) • 5-parameter Nelder-Mead Simplex optimization achieving $\text{PM}=55^\circ$, $\text{GM}=20\text{ dB}$, $K_a=120$ ($<1%$ parabolic tracking error)
The-Pianist-Audio-DSP
Polyphonic Audio Synthesis & FFT Noise Cancellation 		Python (NumPy, SciPy FFT/IFFT, SoundDevice, Matplotlib) • Multi-octave harmonic synthesis ($44.1\text{ kHz}$) & blind Hermitian-symmetric DFT peak cancellation

Technical Skills

  • HDLs & Digital Hardware: VHDL (Pure RTL, Pipelined Datapaths, AXI4-Stream, Custom BRAM/LUT Primitives, CFGLUT5, Dadda Trees, CDC), Xilinx Vivado, ZedBoard (Zynq-7000 SoC), Digilent Nexys 4 (Artix-7 FPGA), Embedded PetaLinux.
  • EDA, Photonics & Physics Simulation: Ansys Lumerical (FDTD, MODE, DGTD, INTERCONNECT), CST Microwave Studio (3D EM), Silvaco Atlas (TCAD), Keysight ADS, KiCad, Proteus SPICE, MATLAB & Simulink.
  • Embedded & Software Engineering: C/C++, Python (NumPy, TensorFlow/Keras, TFLite, SciPy, OpenCV, YOLOv8), 8086 Assembly, Linux/Bash, Git, SPI / I2C / UART / AXI-DMA / MQTT (TLS).

Popular repositories Loading

  1. ZiadAbaid ZiadAbaid Public

    Config files for my GitHub profile.

  2. FPGA-CNN-Inference-Accelerator FPGA-CNN-Inference-Accelerator Public

    5-Layer Q8.8 Fixed-Point Streaming CNN Accelerator in Pure VHDL RTL on Artix-7 FPGA (Nexys 4) with Raspberry Pi 5 8 MHz SPI Co-Design (100% Bit-Exact Parity, 15x Cycle Reduction)

    TeX

  3. Smart-Medical-IoMT-System Smart-Medical-IoMT-System Public

    Distributed Internet of Medical Things (IoMT) Ecosystem: ESP32 Real-Time PPG/IMU Biomedical DSP & Fall Detection with Raspberry Pi 5 TLS-MQTT Telemetry Dashboard

    C++

  4. Silicon-Photonics-Ring-Resonators Silicon-Photonics-Ring-Resonators Public

    Silicon Photonics Modeling & Coupled Microring Resonator Circuit Simulation in Ansys Lumerical (FDTD, MODE, INTERCONNECT) & Automated Optical Fiber Alignment

  5. RF-Analog-Semiconductor-Engineering RF-Analog-Semiconductor-Engineering Public

    Hardware Design & TCAD/EM Simulation Portfolio: 5 GHz 7th-Order Chebyshev Microstrip LPF (CST 3D EM), InGaP QW/SCH/BH Laser Diode Optimization (Silvaco Atlas), and 4-Stage Class-AB BJT Audio Amplif…

    MATLAB

  6. Lead-Lag-Control-System-Optimization Lead-Lag-Control-System-Optimization Public

    Closed-Loop Control System Modeling, Nelder-Mead Simplex Optimization & Lead-Lag Compensator Synthesis in MATLAB & Simulink

    MATLAB