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YashikaSharmaa/README.md

Hi there 👋 I am Yashika Sharma

ECE and Data Science Undergrad

Github Visitors

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  1. Single_Cycle_RISC_V_Processor Single_Cycle_RISC_V_Processor Public

    A Verilog implementation of RISC-V Processor designed for Xilinx Artix-7 FPGA Basys3 board. It features a single-cycle datapath, demonstrating fundamental stages of a of computer architecture: Fetc…

    Verilog

  2. Hospital-Outreach-Analytics Hospital-Outreach-Analytics Public

    BDM Capstone Project focused on spatial and demographic analysis of hospital registration data to identify patient footfall trends, uncover outreach gaps, and support data-driven healthcare outreac…

    1