I work on FPGA and embedded systems, with an emphasis on signal processing, hardware/software co-design, and reproducible development workflows.
My current projects cover FPGA signal processing, Zynq PS + PL systems, STM32 dual-core development, and ESP32-S3 connected devices. Most repositories include build scripts, simulation or self-test entry points, and practical hardware documentation.
我主要从事 FPGA 与嵌入式系统开发，关注信号处理、软硬件协同设计和可复现的开发流程。目前的项目涵盖 FPGA 信号处理、Zynq PS + PL 系统、STM32 双核开发和 ESP32-S3 联网设备，大多数仓库都提供构建脚本、仿真或自测入口，以及必要的硬件说明。
- FPGA architecture, RTL design, simulation, timing closure, and on-board debugging / FPGA 架构、RTL 设计、仿真、时序收敛与板级调试
- Digital signal processing, high-speed ADC acquisition, filtering, and spectrum analysis / 数字信号处理、高速 ADC 采集、滤波与频谱分析
- Zynq hardware/software co-design with Vivado and Vitis / 基于 Vivado 与 Vitis 的 Zynq 软硬件协同设计
- STM32 and ESP32 firmware, reproducible toolchains, and hardware-in-the-loop workflows / STM32 与 ESP32 固件、可复现工具链和硬件在环流程
- Reviewable and deterministic AI-assisted engineering workflows / 可审查、结果可控的 AI 辅助工程流程
Verilog/SystemVerilog · C/C++ · Tcl · Python · PowerShell
Vivado/Vitis · Pango Design Suite · STM32CubeMX · ESP-IDF · CMake · GitHub Actions
If you are working on FPGA signal processing, embedded development templates, or electronic-design competition projects, feel free to open an issue or start a discussion in the relevant repository.
如果你也在研究 FPGA 信号处理、嵌入式开发模板或电子设计竞赛项目，欢迎在对应仓库提交 Issue 或发起 Discussion。