Asynchronous FIFO

A parameterized asynchronous FIFO in SystemVerilog, using Gray-coded pointers and two-flop synchronizers for safe clock domain crossing. Includes a self-checking testbench with a scoreboard, SVA assertions, and functional coverage.

The core architecture follows Clifford E. Cummings' classic paper on asynchronous FIFO design (see References). almost_full and almost_empty threshold flags are an addition on top of that base design.

Features

• Parameterized data width (WIDTH) and depth (DEPTH, must be a power of 2)
• Independent read and write clock domains, each with its own reset
• Gray-coded read/write pointers, synchronized across domains with 2-flop synchronizers
• Registered wfull / rempty flags, glitch-free by construction
• almost_full (fill level >= 3/4 depth) and almost_empty (fill level <= 1/4 depth)

Files

rtl/
  async_fifo.sv      top-level module, wires the submodules together
  fifomem.sv         dual-port memory array (synchronous write, async read)
  wptr_handler.sv    write pointer, wfull, almost_full
  rptr_handler.sv    read pointer, rempty, almost_empty
  synchronizers.sv   sync_r2w / sync_w2r: 2-flop CDC synchronizers
verif/
  async_fifo_tb.sv   self-checking testbench (scoreboard, SVA, coverage)
  dpi/               DPI-C golden model, checker, and testbench
  classes/           class-based testbench (interfaces, transaction, monitor, scoreboard)
  common/            bug-injectable DUT variant shared by dpi/ and classes/
DESIGN.md            design spec with citations
VERIFICATION_PLAN.md architecture, methodology, and checking plan
TESTPLAN.md          detailed test-case list
Makefile             VCS/Verdi build and simulation targets

Verification

This design is checked three independent ways, each a separate testbench built on the same design and largely the same stimulus:

• Scoreboard, SVA, coverage (verif/async_fifo_tb.sv): a reference queue tracks every write and checks it against the corresponding read; SVA covers reset behavior, wfull/rempty mutual exclusion, pointer stall-on-full/empty, and threshold-correct almost_full/almost_empty; covergroups track fill-level bins, full/empty transitions, concurrent read/write crossing, and clock ratio combinations.
• DPI-C golden model (verif/dpi/): a C reference model is called from SystemVerilog on every write/read pin toggle and compared against the DUT, independent of the SV scoreboard above.
• Class-based scoreboard (verif/classes/): write-side and read-side interfaces, a transaction class, a monitor per clock domain posting to a mailbox, and a scoreboard class pulling from it and checking against a reference queue.

The DPI and class-based testbenches both run against verif/common/async_fifo_bug.sv, a drop-in DUT variant with a plusarg-gated dropped-write bug (+inject_bug +drop_every=N), used to demonstrate that each checker actually catches a real fault and isn't just passing by construction. See make dpi_clean / make dpi_bug / make class_clean / make class_bug.

See VERIFICATION_PLAN.md for the testbench architecture, methodology, and checking plan, and TESTPLAN.md for the detailed test-case list.

References

1. Clifford E. Cummings, "Simulation and Synthesis Techniques for Asynchronous FIFO Design," SNUG (Synopsys Users Group) 2002, San Jose, CA. sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf