Hi, Iโm Sriram Vaibhav ๐ย
ECE undergrad at IIIT Nagpur | VLSI & FPGA enthusiast | Currently interning at ISRO, working on digital comms and hardware design ๐ | Skills: Verilog, SystemVerilog, C, C++, Python.
Hi! I am Sriram Vaibhav currently pursuing my B.Tech at IIIT Nagpur. I thrive on the exhilarating journey of learning and seeking fresh perspectives.
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FPGA Intern @BitMapper Integration, Project Intern @nrsc, ISRO
Popular repositories Loading
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gini-agent
gini-agent PublicForked from Open-Curiosity/gini-agent
The agent that remembers and learns.
TypeScript
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RedKnot
RedKnot PublicForked from rednote-machine-learning/RedKnot
Efficient Long-Context LLM Serving with Head-Aware KV Reuse and SegPagedAttention
Python
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