Name		Name	Last commit message	Last commit date
debug		debug
fpga		fpga
rtl		rtl
tb		tb
tests		tests
.gitattributes		.gitattributes
.gitignore		.gitignore
CONTRIBUTING.md		CONTRIBUTING.md
LICENSE		LICENSE
README.md		README.md

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SPI Slave

SPI Slave mode 0 written in SystemVerilog

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SPI Slave module written in SystemVerilog HDL

fpga openhardware spi spislave systemverilog systemverilog-hdl verilog verilog-hdl

CERN-OHL-P-2.0 license

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