SARV is a 32-bit RISC-V processor implementing the RV32I base ISA together with selected standard extensions including Bit Manipulation (B), Compressed Instructions (C), Zmmul, Zicond, and Zicsr.
The core is written in Verilog HDL and targets FPGA and ASIC implementations. It is designed as a compact embedded processor with a modular RTL architecture.
- Architectural & ABI Comparisons
- CSR & interrupts
- Critical Path
- Power Control
- Branch Prediction
- Return Address Stack
| Extension | Description | Status |
|---|---|---|
| RV32I | Base Integer Instructions | Full |
| Zmmul | Integer Multiplication (no division) | Full |
| Zicond | Conditional Operations | Full |
| Zihintpause | Pause Hint Instruction | Full |
| Sub-extension | Description | Status |
|---|---|---|
| Zca | Integer Compressed Instructions | Full |
| Zcb | Additional Compressed Instructions | Full |
| Sub-extension | Description | Status |
|---|---|---|
| Zba | Address Generation | Full |
| Zbb | Basic Bit-Manipulation | Full |
| Zbs | Single-Bit Operations | Full |
| Zbc | Carry-less Multiplication | Full |
| Extension | Description | Status |
|---|---|---|
| Zicsr | Control Status Registers | Full |
| Zihpm | Hardware Performance Monitors | Full |
| Type | Description | Status |
|---|---|---|
| MEI | Machine External Interrupt | Supported |
| MTI | Machine Timer Interrupt | Supported |
| MSI | Machine Software Interrupt | Supported |
| Feature | Description | Status |
|---|---|---|
| WFI | Wait for Interrupt — halts core until IRQ | Supported |
| Metric | Value |
|---|---|
| CoreMark | 1508.755307 |
| Frequency | 500 MHz (simulated) |
| CoreMark/MHz | 3.017510614 |
| Simulation | Gate-level, ideal memory |
| Flags | -march=rv32ib_zicond_zmmul_zicsr_zca -mabi=ilp32 -Ofast |
Measured in gate-level simulation without cache/memory latency. Provides architectural comparison point.
The design under test uses a Branch Target Buffer (BTB) with 8 entries (BRANCH_PREDICTION_ENTRY_INDEX_BITS = 3) and a Return Address Stack (RAS) with 2 entries (RETURN_ADDRESS_PREDICTION_ENTRY_INDEX_BITS = 1).
| Test Suite | Status |
|---|---|
| CoreMark | Pass |
| Custom tests | Pass |
| Metric | Value |
|---|---|
| Total Area | 34,881.644 µm² |
| Cell Count | 24,463 |
| KGE | 13.105 kGE |
| Flip-Flops (DFFR/DFFS) | 2730 |
| Synthesis Tool | Yosys |
| Post-synthesis estimated Fmax | 550 MHz |
The figure below shows the top level organization of the SARV core. Detailed down to wire and module documentation are available in the docs/ directory.
The SARV core has been tested using:
- Simulator: QuestaSim 2024.1
vlog rtl/*.vvsim work.tb_top
run -allNote: Before running the simulation, update the instruction memory initialization file (
memory.txt) to point to your desired program image and current path.
SARV is licensed under the CERN Open Hardware Licence Version 2 – Strongly Reciprocal (CERN-OHL-S-2.0).
You are free to use, modify, and manufacture hardware based on this project, provided you comply with the terms of the CERN-OHL-S v2.
See the LICENSE file for details.