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Rex-Josaphat/RISCV-Multicycle-Processor

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This repository includes the code used for the design and implementation of a RISC-V Mutlicycle Processor. The repository contains all modules for the controller, ALU and ALU Decoder as well as the top module to integrate all functions. It also has testbenches for simulating the functionality.

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SystemVerilog files for modules and testbench for the RISC-V Multicycle Processor

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