Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
simulation/questa		simulation/questa
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md
VHDL_testing.bdf		VHDL_testing.bdf
VHDL_testing.qpf		VHDL_testing.qpf
VHDL_testing.qsf		VHDL_testing.qsf
dl.bsf		dl.bsf
dl.vhd		dl.vhd
flpenr.bsf		flpenr.bsf
flpenr.vhd		flpenr.vhd
flpr.bsf		flpr.bsf
flpr.vhd		flpr.vhd
fulladder.bsf		fulladder.bsf
fulladder.vhd		fulladder.vhd
fulladderw.bsf		fulladderw.bsf
fulladderw.vhd		fulladderw.vhd
seven_seg_decoder.bsf		seven_seg_decoder.bsf
seven_seg_decoder.vhd		seven_seg_decoder.vhd
sync_two_dff.bsf		sync_two_dff.bsf
sync_two_dff.vhd		sync_two_dff.vhd
sync_two_dffw.bsf		sync_two_dffw.bsf
sync_two_dffw.vhd		sync_two_dffw.vhd

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learning_VHDL

just a lil messing around using VHDL :)

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