Add common-rtl submodule for global package and Update Submodules - #2
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KietLe11
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icabuent
approved these changes
Apr 22, 2026
icabuent
approved these changes
Apr 22, 2026
📊 Hardware Synthesis MetricsTarget Top:
|
| Metric | Target | Value |
|---|---|---|
| Logic | FPGA (Xilinx LUTs) | N/A LUTs |
| Memory | FPGA (18K BRAMs) | 0 Blocks |
| Area | ASIC (CMOS2) | N/A GEs |
| Timing | Critical Path | N/A Logic Levels |
Generated automatically by the centralized Yosys + Slang CI Pipeline.
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