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Implement LSRS Instruction#21

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lmSeryi merged 8 commits into
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feat/lsrs
Feb 9, 2026
Merged

Implement LSRS Instruction#21
lmSeryi merged 8 commits into
masterfrom
feat/lsrs

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@begeistert

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Description

  • Fix LSLS register shift behavior: set N and Z when shift is zero and compute carry from the shifted-out bit (do not reuse previous C).
  • Implement missing LSRS variants: LsrsImm5 (imm 1–31), LsrsImm32 (imm #0 treated as shift 32/zero result), and LsrsRegister (register-specified shifts) with correct N, Z, and C updates and safe carry computation for edge cases (shift >= 32).
  • Decoder: add LSRS immediate-5, immediate-32, and register encodings; reorder LSLS zero rule so register forms match before zero-rule.
  • Assembler: add InstructionEmitter helpers LsrsImm5 and LsrsRegister with validation for low-register indices and immediate ranges.
  • Tests: add LSRS tests and extend LSLS tests to cover edge cases (shift >32, immediate 0 as 32, carry behavior, shift-register operand as unsigned byte) and include LSRS encodings in the decoder test matrix.

Type of change

  • 🐛 Bug fix (non-breaking change which fixes an issue)
  • ✨ New feature (non-breaking change which adds functionality)
  • 💥 Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • 🧹 Refactoring (no functional changes, just code cleanup)

Checklist

  • 🧪 Tests passed locally (dotnet test)
  • ✅ Added new tests for this feature/fix
  • 📝 Documentation updated (if applicable)
  • 🚫 No "Magic Strings" or hardcoded values
  • 💾 Validated against the RP2040 Datasheet (if applicable)

Screenshots / Hex Dumps (Optional)

Fix LSLS register shift behavior to set N and Z shift is
zero and to compute carry from the shifted-out bit instead of
reusing the previous C flag. Add missing LSRS implementations:
- LsrsImm5 for shifts 1-31
- LsrsImm32 for #0 (treated as shift 32/zero result)
- LsrsRegister for register-specified shifts

These changes ensure correct N, Z, and C updates for logical
shift right/left operations, handle the zero-shift fast path,
and compute carry bits safely for edge cases (shift >= 32).
Add support for LSRS register and immediate-32 encodings and register the
LSRS immediate-5 opcode. Reorder the LSLS zero rule to maintain correct
matching precedence among shift instructions.

Why:
- LSRS (register) T2 missing and is now mapped to BitOps.LsrsRegister,
  enabling register-based logical right shifts.
- A special LSRS imm #32 case is handled via BitOps.LsrsImm32 to match
  ARM semantics for a shift of 32 producing defined results.
- LSRS immediate-5 is added so immediate-form logical right shifts decode
  correctly.
- LSLS zero rule is moved after the register forms to ensure more specific
  encodings are matched first and avoid accidental trapping of other
  shift encodings.
Add two new helper emitters to InstructionEmiter: LsrsImm5 and
LsrsRegister. LsrsImm5 encodes the logical shift right (immediate)
variant with a 5-bit immediate and validates low-register indices and
immediate range. LsrsRegister encodes the register-specified LSRS form
and validates low-register indices.

These helpers mirror existing shift encoders, provide consistent
argument validation, and enable emitting LSRS instructions from higher
level code.
Extend bitwise shift instruction tests to cover missing edge cases
and ensure correct decoder/test table entries.

- Add LSRS instruction entries to InstructionDecoderTests to include
  immediate, immediate-as-32, and register forms in the decoder test
  matrix.
- Convert Lsls test class to abstract so both immediate and register
  variants can coexist and be extended.
- Add new Lsls register tests:
  - verify result is zero and carry cleared when shifting by > 32
  - verify shift-register operand is interpreted as an unsigned byte
- Add a new Lsrs test class with immediate-mode tests:
  - basic right shift behavior and PC update
  - immediate 0 interpreted as logical shift by 32
  - explicit carry behavior when a 1 is shifted out
  - shift by maximum immediate (31) coverage

These changes improve coverage for shifts (LSL/LSR) and catch corner
cases around shift widths and carry flag behavior.
@begeistert
begeistert requested a review from lmSeryi as a code owner February 2, 2026 20:44
@begeistert begeistert self-assigned this Feb 2, 2026
@begeistert begeistert added the enhancement New feature or request label Feb 2, 2026
Expand GitHub Actions matrix to include self-hosted runner and
prevent the workflow from failing fast so all matrix jobs run.

Add conditional step to add .NET global tools to PATH on the
self-hosted runner, fixing missing tool availability when using
self-hosted agents. Update job name to show the selected runner.
…it Actions unit-tests by collapsing the runner

matrix into a single `runs-on` array and removing the explicit matrix
strategy and runner name. This reduces workflow verbosity while
preserving execution on both `ubuntu-latest` and `self-hosted` runners.
Remove conditional "Self-Hosted fix" check from the GitHub Actions test
workflow and rename the step to "Add .NET tools to PATH". The step now
always appends the .dotnet tools path to GITHUB_PATH instead of running
only for self-hosted runners.

This ensures the dotnet tools path is consistently available regardless
of runner type and reduces conditional complexity in the workflow.
Change the GitHub Actions workflow to use the hosted ubuntu-latest
runner instead of an array included self-hosted. Remove an
unnecessary step that attempted to add .NET global tools to PATHsince the workflow does not rely on that step and dotnet tools are not
required for the scanner installation in this context.

This simplifies runner selection, avoids accidentally scheduling jobs
on self-hosted machines, and cleans up redundant steps to make the CI
flow clearer and more robust.
@sonarqubecloud

sonarqubecloud Bot commented Feb 3, 2026

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@lmSeryi
lmSeryi merged commit 94d3ade into master Feb 9, 2026
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