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Add implementation and decoding for the TST (Rn, Rm) instruction, including: - Instruction handler in BitOps.Tst that computes Rn & Rm and updates the N and Z flags. - Opcode rule for TST in InstructionDecoder to route 0x4200 pattern to BitOps.Tst. - InstructionEmiter.Tst helper to emit the 16-bit TST opcode for low registers and argument validation for low-register constraints. Add unit tests in BitOpsTests: - Should_SetNegativeFlag_When_ResultHasSignBitSet verifies N is set when the bitwise AND has the sign bit. - Should_SetZeroFlag_When_ResultIsZero verifies Z is set when result is zero. Tighten register index validation in InstructionEmiter.Rsbs: - Change high/low register bounds checks to use low-register range (0-7) and throw LowRegisterIndexOutOfRange for low-register encodings. These changes implement bit-test functionality, ensure the decoder recognizes the instruction, and add tests to validate flag behavior.
Add unit tests for three previously untested ARM instructions in the InstructionDecoder suite: Rev16, Movs and Tst. These are added alongside existing bit-op and move variations to ensure the decoder emits the correct encodings and the corresponding BitOps handlers are validated. This improves coverage for byte/halfword reversal and flag-affecting move/test operations, catching decoder regressions and aligning tests with implemented instruction emitters.
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lmSeryi
approved these changes
Feb 9, 2026
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