Ssi splitter

common/hdl/delay_filter.vhd

@@ -38,9 +38,6 @@ signal pulse_buf        : std_logic_vector(2 downto 0) := "000";
 signal filt             : std_logic := '0';
 signal jk               : std_logic_vector(1 downto 0);
 
-attribute async_reg     : string;
-attribute async_reg of pulse_buf : signal is "TRUE";
-
 begin
 
 --------------------------------------------------------------------------

common/hdl/iobuf_registered.vhd

@@ -32,18 +32,38 @@ architecture rtl of iobuf_registered is
 signal ipad     : std_logic;
 signal opad     : std_logic;
 
+attribute IOB : string;
+attribute IOB of ipad : signal is "TRUE";
+attribute ASYNC_REG : string;
+attribute ASYNC_REG of opad : signal is "TRUE";
+
+signal tied_to_ground : std_logic := '0';
+signal tied_to_vcc    : std_logic := '1';
+
 begin
 
 --------------------------------------------------------------------------
 -- Register and pack into IOBs
 --------------------------------------------------------------------------
 process(clock) begin
     if rising_edge(clock) then
-        O <= opad;
         ipad <= I;
     end if;
 end process;
 
+IDDR_inst : IDDR
+    generic map (
+        DDR_CLK_EDGE => "SAME_EDGE_PIPELINED")
+    port map (
+        Q1 => O,
+        Q2 => open,
+        C => clock,
+        CE => tied_to_vcc,
+        D => opad,
+        R => tied_to_ground,
+        S => tied_to_ground
+);
+
 -- Physical IOBUF instantiations controlled with PROTOCOL
 IOBUF_inst : IOBUF
 port map (

common/templates/top_defines.vhd.jinja2

@@ -44,6 +44,7 @@ constant EBUSW              : natural := 12;
 --------------------------------------------------------------------------
 
 constant DCARD_MONITOR      : std_logic_vector(2 downto 0) := "011";
+constant DCARD_MON_CTRL     : std_logic_vector(2 downto 0) := "010";
 
 type t_mode_group is array (5 downto 0) of std_logic_vector(31 downto 0);
 type t_mode is array (PBUSW-1 downto 0) of t_mode_group;

targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd

@@ -52,6 +52,8 @@ begin
             return X"0C";
         when "011"  => -- EnDat
             return X"14";
+        when "110" => -- SSI-splitter
+            return X"03"; -- same as Incremental
         when others =>
             return X"00";
     end case;
@@ -72,22 +74,25 @@ begin
             return X"07";
 		when "101" => -- Data passthrough (same as SSI)
 			return X"28";
+        when "110" =>  -- SSI-splitter
+            return X"07"; -- same as Incremental
         when others =>
-            return X"00";
+            return X"04";
     end case;
 end OUTENC_CONV;
 
-function CONV_PADS(INENC, OUTENC : std_logic_vector) return std_logic_vector is
+function CONV_PADS(INENC, OUTENC, DCARD_MODE : std_logic_vector) return std_logic_vector is
     variable enc_ctrl_pad : std_logic_vector(11 downto 0);
 begin
 
     enc_ctrl_pad(1 downto 0) := INENC(1 downto 0);
     enc_ctrl_pad(3 downto 2) := OUTENC(1 downto 0);
-    enc_ctrl_pad(4) := INENC(2);
+    enc_ctrl_pad(4) :=  not INENC(2) when DCARD_MODE(3 downto 1) = DCARD_MON_CTRL else INENC(2);
     enc_ctrl_pad(5) := OUTENC(2);
     enc_ctrl_pad(7 downto 6) := INENC(4 downto 3);
     enc_ctrl_pad(9 downto 8) := OUTENC(4 downto 3);
-    enc_ctrl_pad(10) := INENC(5);
+    enc_ctrl_pad(10) := '1' when (DCARD_MODE(3 downto 1) = DCARD_MONITOR
+      or DCARD_MODE(3 downto 1) = DCARD_MON_CTRL) else INENC(5);
     enc_ctrl_pad(11) := OUTENC(5);
 
     return enc_ctrl_pad;
@@ -133,10 +138,10 @@ begin
 end process;
 
 -- Interleave Input and Output Controls to the Daughter Card Pins.
-dcard_ctrl1_io(11 downto 0) <= CONV_PADS(inenc_ctrl(0), outenc_ctrl(0));
-dcard_ctrl2_io(11 downto 0) <= CONV_PADS(inenc_ctrl(1), outenc_ctrl(1));
-dcard_ctrl3_io(11 downto 0) <= CONV_PADS(inenc_ctrl(2), outenc_ctrl(2));
-dcard_ctrl4_io(11 downto 0) <= CONV_PADS(inenc_ctrl(3), outenc_ctrl(3));
+dcard_ctrl1_io(11 downto 0) <= CONV_PADS(inenc_ctrl(0), outenc_ctrl(0), DCARD_MODE_i(0));
+dcard_ctrl2_io(11 downto 0) <= CONV_PADS(inenc_ctrl(1), outenc_ctrl(1), DCARD_MODE_i(1));
+dcard_ctrl3_io(11 downto 0) <= CONV_PADS(inenc_ctrl(2), outenc_ctrl(2), DCARD_MODE_i(2));
+dcard_ctrl4_io(11 downto 0) <= CONV_PADS(inenc_ctrl(3), outenc_ctrl(3), DCARD_MODE_i(3));
 
 DCARD_MODE <= DCARD_MODE_i;
 

targets/PandABox/blocks/inenc/inenc.block.ini

@@ -1,6 +1,7 @@
 [.]
 description: Input encoder
 entity: inenc
+ip: ila_32x8K
 
 [CLK]
 type: bit_mux
@@ -13,6 +14,7 @@ description: Type of absolute/incremental protocol
 1: SSI
 2: BISS
 3: enDat
+6: SSI-Splitter
 
 [CLK_SRC]
 type: param enum
@@ -48,6 +50,14 @@ description: Set point
 type: param bit
 description: Zero position on Z rising edge
 
+[DEBOUNCE_EN]
+type: param bit
+description: Enable optional debouncing for clock input lines
+
+[DEBOUNCE_TIME]
+type: param uint 127
+description: Time constant in clock ticks for debounce timeout 
+
 [A]
 type: bit_out
 description: Quadrature A if in incremental mode
@@ -91,7 +101,7 @@ type: read enum
 description: Daughter card jumper mode
 0: DCARD id 0
 1: Encoder Control
-2: DCARD id 2
+2: Encoder Mon+Ctrl
 3: Encoder Monitor
 4: DCARD id 3
 5: DCARD id 4

targets/PandABox/blocks/outenc/outenc.block.ini

@@ -37,6 +37,7 @@ description: Type of absolute/incremental protocol
 3: enDat
 4: ABZ Passthrough
 5: DATA Passthrough
+6: SSI-Splitter
 
 [BITS]
 type: param uint 32
@@ -66,7 +67,7 @@ type: read enum
 description: Daughter card jumper mode
 0: DCARD id 0
 1: Encoder Control
-2: DCARD id 2
+2: Encoder Mon+Ctrl
 3: Encoder Monitor
 4: DCARD id 3
 5: DCARD id 4