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- #4556 · NewPaulWalker opened
on Apr 14, 2025 1 - #4242 · castleberrysam opened
on Feb 2, 2025 11
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mstatus.VSDirty update forvl=0vector memory instructionsmodule: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6561 In OpenXiangShan/XiangShan;vssubu.vx(vector fixed-point unsigned saturating subtract) does not setvxsatwhen it saturates — kunminghu-v3module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6555 In OpenXiangShan/XiangShan;vsrl.vvwithv0.tmask hangs and never writes back the destination registermodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6545 In OpenXiangShan/XiangShan;vcpop.mis incorrectly reported as an illegal instruction whenLMUL=8andvs2is not group-alignedmodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6544 In OpenXiangShan/XiangShan;vdiv.vxwith a zero divisor deadlocks the coremodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6543 In OpenXiangShan/XiangShan;stvalmismatch on a scalar store **page** fault after a vector store **page** fault (S-mode) — kunminghu-v2module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedversion: kunminghu-v2Issue or PR to the stable release kunminghu-v2Issue or PR to the stable release kunminghu-v2Status: Open.#6540 In OpenXiangShan/XiangShan;vmadc.vizeroes mask-destination tail bitsmodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6536 In OpenXiangShan/XiangShan;haltreq / resethaltreq out of reset: no dedicated halt path, hart may commit instructions before entering Debug Mode
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6505 In OpenXiangShan/XiangShan;[Bug]
csrw minstret, Xfollowed bycsrrreads X+1: the writing instruction's own retirement is added after the writemodule: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6501 In OpenXiangShan/XiangShan;WFI woken by an interrupt: if the next instruction is a load/store/CSR/fence it executes before the trap is taken (mepc = wfi+6/+8 instead of wfi+4)
module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuantype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6500 In OpenXiangShan/XiangShan;Misaligned load/store whose second half crosses into the non-canonical Sv39/Sv48 hole is not page-faulted; the high half aliases to the upper-half mapping
module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/confirmed(issue) Bug reports that are confirmed(issue) Bug reports that are confirmedStatus: Open.#6498 In OpenXiangShan/XiangShan;Legal segmented store
vsseg2e16.vsilently commits wrong store data (0 instead of the source value) — vector store-data unit emits 0 for a field on kunminghu-v3version: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6486 In OpenXiangShan/XiangShan;