docs: tell Hi3518EV200 owners to check DDR2 vs DDR3 before flashing - #493
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This SoC ships with either kind of memory, and OpenIPC now publishes a bootloader for each. They are not interchangeable: the DRAM type is fixed in a register table inside the image, so the wrong one leaves the board with no working memory at all. It flashes and verifies perfectly and then boots nothing, which reads as a bad flash or a dead chip and is neither. That is a week of debugging for the person it happens to -- see OpenIPC/firmware#2299, where it took a UART recovery session and a register dump out of the vendor bootloader to identify. `md.l 0x20111050 1` from any working HiSilicon U-Boot answers it in one command, so put it next to the flashing instructions rather than leaving people to find out afterwards. Also warns against telling the two images apart by size or checksum: the build embeds a timestamp, so both change between builds of identical sources and the sizes have already been observed to swap round. Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
This was referenced Aug 27, 2026
PR Summary by QodoDocument DDR2/DDR3 bootloader selection for Hi3518EV200
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Follow-up to OpenIPC/u-boot-hi3516cv200#9, which started publishing
u-boot-hi3518ev200-ddr3-{universal,recovery}.bin.Hi3518EV200 boards ship with either DDR2 or DDR3, and the bootloaders are
not interchangeable — the DRAM type is fixed in a register table baked
into the image, so the wrong one leaves the board with no working memory
at all. The failure is nasty precisely because it looks like something
else: the flash writes and verifies byte-for-byte, and then nothing
boots.
In OpenIPC/firmware#2299 that cost the reporter about a week, a UART
recovery session and a register dump out of their vendor bootloader
before we worked out that the board was DDR3 and every OpenIPC
hi3518ev200 image was DDR2.
md.l 0x20111050 1from any working HiSilicon U-Boot — including thevendor's own, before OpenIPC is installed — answers it in one command:
the last hex digit is
5for DDR2 and6for DDR3, perDMC_CFG_DRAM_TYPE_MASKindrivers/ddr/ddr_ddrc_v500.h. This puts thatcheck immediately before the bootloader-flashing commands in the Danger
zone section.
Two other things it says, both learned the hard way in that issue:
generates
U_BOOT_DATE/U_BOOT_TIMEfromdate, so the compressedpayload shifts a few bytes between builds of identical source. The
published DDR2 and DDR3 sizes have already swapped round once between
two builds an hour apart.
-recovery.binis not a thing to flash. It is built to fit theboot ROM's SRAM window for UART upload to a board that will not boot.
Rendered wording is in the diff; no existing text is changed, only
inserted ahead of the
mw.b/tftp/sf writeblock.