Disable SVB for hi3516av200 to fix DDR instability - #2
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CONFIG_SVB_ENABLE adjusts CPU/DDR voltages after DDR initialization, destabilizing memory at higher addresses. The vendor firmware does not enable SVB. Confirmed by binary analysis and real hardware testing. Camera: Hi3516AV200 + 512MB DDR + SPI NAND MX35LF1GE4AB Fixes: OpenIPC/firmware#517 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Closing — the root cause was not SVB but SPL size truncation. With SVB enabled, The proper fix is in defib (OpenIPC/defib#55): dynamically detect SPL code size from the LZMA boundary instead of using the hardcoded profile value. Verified on hardware — SVB-enabled U-Boot boots and pings successfully with the defib fix. |
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Summary
Disable
CONFIG_SVB_ENABLEfor hi3516av200 (SPI NOR and NAND configs).Root cause
start_svb()runs at the beginning ofstart_ddr_training()and adjusts CPU/DDR voltages via HPM readings after the.regtable has already initialized DDR. This causes DDR to work at low addresses (0x81000000) but fail at higher addresses (0x88300000, TEXT_BASE), crashing the mini-boot.The vendor firmware does not have SVB enabled — binary analysis shows zero references to the PMC register block (0x120A0000) in the vendor SPL.
Test plan
arm-hisiv500-linux-toolchain — boots with 512MB RAM detectedFixes: OpenIPC/firmware#517
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