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Verilog attributes not kept when verilog is generated

Status: Open.

#206 In Nic30/hdlConvertor;

· fjullien opened on Sep 18, 2025

HDLConverter - Project Issue in parsing assign statement

Status: Open.

#198 In Nic30/hdlConvertor;

· nitinhariharan opened on Mar 13, 2025

Package and Interface level information is missing

Status: Open.

#196 In Nic30/hdlConvertor;

· nitinhariharan opened on Mar 10, 2025

Prebuilt Binary Release to PyPi

Status: Open.

#187 In Nic30/hdlConvertor;

· khwong-c opened on Jan 5, 2024

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v2.4

(System)Verilog parallel_case attribute is not supported

Status: Open.

#185 In Nic30/hdlConvertor;

· KatCe opened on Oct 17, 2023

Using updated SV/Verilog, VHDL Grammars

Status: Open.

#178 In Nic30/hdlConvertor;

· AmeyaVS opened on Apr 17, 2023

Updating Git Submodules For Tests

Status: Open.

#177 In Nic30/hdlConvertor;

· AmeyaVS opened on Apr 16, 2023

Verilog2017 - unpacked array converted as packed

Status: Open.

#169 In Nic30/hdlConvertor;

· diffore opened on Jun 14, 2022

Convert VHDL package to Verilog or SV

Status: Open.

#168 In Nic30/hdlConvertor;

· jabate-anova opened on Apr 5, 2022

incorrect Position

Status: Open.

#166 In Nic30/hdlConvertor;

· Thomasb81 opened on Feb 5, 2022

Preprocessor - expose complete parser?

Status: Open.

#165 In Nic30/hdlConvertor;

· the-moog opened on Dec 24, 2021

Handling extraneous commas (SystemVerilog)

Status: Open.

#163 In Nic30/hdlConvertor;

· the-moog opened on Nov 26, 2021