0dMIPS v0.1 "Doragate"

Initial public release of a MIPS64r6 SoC soft-core implemented in SystemVerilog, simulated with Verilator and verified with GTest.

This release covers the core pipeline, L1 caches, CP0 exceptions, MMIO peripherals (VGA, Timer, LED, mock stdout), and a TUI debugger. see the roadmap (https://github.com/Nambers/0dMIPS/milestones) for what's planned.