Welcome to the Digital Design Lab Submissions Repository.
This repository will serve as the submission portal for all lab deliverables throughout the week. Students are required to follow the given structure and guidelines strictly while submitting their work.
The course is structured around a progressive lab manual that introduces SystemVerilog-based Digital Design concepts and FPGA synthesis methodology. The labs (the lab manual is attached here) are divided into combinational, sequential, FSM, interface, and integration-based designs.
- Introduction to Digital Design Methodology
- Design Flow Overview, Principles, Documentation Requirements
- SystemVerilog Fundamentals for Digital Design
- Constructs, Data Types, Always Blocks, Synthesis Guidelines
- Lab 1: Basic Combinational Circuits
- 8-bit ALU
- Priority Encoder with Enable
- Lab 2: Advanced Combinational Logic
- 32-bit Barrel Shifter
- Binary Coded Decimal (BCD) Converter
- Lab 3: Sequential Circuit Fundamentals
- Programmable Counter
- Lab 4: Finite State Machines
- Traffic Light Controller
- Vending Machine Controller
- Lab 5: Counters and Timers
- Multi-Mode Timer
- Lab 6: Memory Interfaces
- Synchronous SRAM Controller
- Lab 7: FIFO Design
- Synchronous FIFO
- Asynchronous FIFO (CDC)
- Lab 8: UART Controller
- UART Transmitter
- UART Receiver
- Lab 9: SPI Controller
- SPI Master Controller
- Lab 10: AXI4-Lite Interface Design
- AXI4-Lite Slave Design
- Protocol Compliance & Performance
- FPGA Synthesis Guidelines
- Synthesis-Friendly Coding, Constraints, Resource/Timing Reports
- Design Documentation Standards
- Block Diagrams, FSM Documentation, Timing Diagrams, Interface Specs
- Lab Exercise Guidelines
- Pre-Lab Prep, During Lab, Post-Lab, Grading
- Additional Resources
- Recommended Reading, Tools, Software, Online Resources
- Each student must fork this repository and create a folder with their roll number or name.
- Place your deliverables in the folder structure:
<Your_Folder_Name>/
|- Lab-XX/
||-- \<your\_code>.sv <testbench>.sv
||-- documentation.pdf
||-- synthesis\_reports/
||-- <Output waveform screenshot>
|- Lab-XY/
----
- Documentation Requirements (Compulsory):
- Block diagrams
- State diagrams (for FSM labs)
- Timing diagrams (where applicable)
- Interface specifications (AXI4-Lite, UART, SPI, etc.)
YOUR FOLDER/
|- Lab-01A-ALU/
||-- alu.sv
||-- tb\_alu.sv
||-- report.pdf
|- Lab-01B-PriorityEncoder/
||-- priority\_encoder.sv
||-- tb\_priority\_encoder.sv
||-- report.pdf
|- Lab-02A-BarrelShifter/
|- Lab-02B-BCDConverter/
...
- Correctness of Design & Functionality
- Code Quality & Synthesis-Friendliness
- Documentation Completeness
- Testbench & Simulation Evidence
- Optimization & Extra Effort
- HDL Language: SystemVerilog
- Simulator: ModelSim / Questa / iverilog + GTKWave
- Synthesis: Xilinx Vivado
- Late submissions will not be entertained unless approved.
- Plagiarism will result in zero marks and disciplinary action.
- Each student must be able to defend their submitted code in viva sessions.