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remove le, and add stpc #2

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18 changes: 9 additions & 9 deletions spec/spec.md → spec.md
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Original file line number Diff line number Diff line change
Expand Up @@ -47,15 +47,15 @@ When an immediate is used as the operand it takes up the entire four bit space o
| add | 0001 | Reg Reg | r0 = op1 + op2 |
| sub | 0010 | Reg Reg | r0 = op1 - op2 |
| ge | 0011 | Reg Reg | r0 = op1 > op2 (1 if true else 0) |
| le | 0100 | Reg Reg | r0 = op1 < op2 (1 if true else 0) |
| inc | 0101 | Reg | op1 = op1 + 1 |
| dec | 0110 | Reg | op1 = op1 - 1 |
| shift | 0111 | Imm | r0 = r0 << imm with some nuance |
| ali | 1000 | Imm | r0 = r0 & imm |
| li | 1001 | Imm | r0 = imm |
| mv | 1010 | Reg Reg | op1 = op2 |
| load | 1011 | Reg Reg | op1 = mem$op2$ |
| store | 1100 | Reg Reg | mem$op2$ = op1 |
| inc | 0100 | Reg | op1 = op1 + 1 |
| dec | 0101 | Reg | op1 = op1 - 1 |
| shift | 0110 | Imm | r0 = r0 << imm with some nuance |
| ali | 0111 | Imm | r0 = r0 & imm |
| li | 1000 | Imm | r0 = imm |
| mv | 1001 | Reg Reg | op1 = op2 |
| load | 1010 | Reg Reg | op1 = mem\[op2\] |
| store | 1011 | Reg Reg | mem\[op2\] = op1 |
| stpc | 1100 | Reg | mem\[op1\] = pc + 2 |
| jmp | 1101 | Imm | pc = imm |
| jiz | 1110 | Reg Reg | if op2 = 0 then pc = pc + op1 |
| jaiz | 1111 | Reg Reg | if op2 = 0 then pc = op1 |
46 changes: 0 additions & 46 deletions spec/idea.md
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38 changes: 19 additions & 19 deletions web_impl/dist/isa.js
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Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,15 @@ var InstructionKind;
InstructionKind[InstructionKind["Inc"] = 3] = "Inc";
InstructionKind[InstructionKind["Dec"] = 4] = "Dec";
InstructionKind[InstructionKind["Ge"] = 5] = "Ge";
InstructionKind[InstructionKind["Le"] = 6] = "Le";
// 4 bit immdiate. If the most significant bit is 1 then right shift, else left shift.
// Shift amount is the remainding 3 bits.
InstructionKind[InstructionKind["Shift"] = 7] = "Shift";
InstructionKind[InstructionKind["Ali"] = 8] = "Ali";
InstructionKind[InstructionKind["Li"] = 9] = "Li";
InstructionKind[InstructionKind["Mv"] = 10] = "Mv";
InstructionKind[InstructionKind["Load"] = 11] = "Load";
InstructionKind[InstructionKind["Store"] = 12] = "Store";
InstructionKind[InstructionKind["Shift"] = 6] = "Shift";
InstructionKind[InstructionKind["Ali"] = 7] = "Ali";
InstructionKind[InstructionKind["Li"] = 8] = "Li";
InstructionKind[InstructionKind["Mv"] = 9] = "Mv";
InstructionKind[InstructionKind["Load"] = 10] = "Load";
InstructionKind[InstructionKind["Store"] = 11] = "Store";
InstructionKind[InstructionKind["Stpc"] = 12] = "Stpc";
InstructionKind[InstructionKind["Jmp"] = 13] = "Jmp";
InstructionKind[InstructionKind["Jiz"] = 14] = "Jiz";
InstructionKind[InstructionKind["Jaiz"] = 15] = "Jaiz";
Expand Down Expand Up @@ -73,52 +73,52 @@ const InstructionInfo = {
encoding: 5,
is_directive: false,
},
[InstructionKind.Le]: {
kind: InstructionKind.Le,
name: "le",
operand_kind: OperandKind.RegReg,
encoding: 6,
is_directive: false,
},
[InstructionKind.Shift]: {
kind: InstructionKind.Shift,
name: "shift",
operand_kind: OperandKind.Imm,
encoding: 7,
encoding: 6,
is_directive: false,
},
[InstructionKind.Ali]: {
kind: InstructionKind.Ali,
name: "ali",
operand_kind: OperandKind.Imm,
encoding: 8,
encoding: 7,
is_directive: false,
},
[InstructionKind.Li]: {
kind: InstructionKind.Li,
name: "li",
operand_kind: OperandKind.Imm,
encoding: 9,
encoding: 8,
is_directive: false,
},
[InstructionKind.Mv]: {
kind: InstructionKind.Mv,
name: "mv",
operand_kind: OperandKind.RegReg,
encoding: 10,
encoding: 9,
is_directive: false,
},
[InstructionKind.Load]: {
kind: InstructionKind.Load,
name: "load",
operand_kind: OperandKind.RegReg,
encoding: 11,
encoding: 10,
is_directive: false,
},
[InstructionKind.Store]: {
kind: InstructionKind.Store,
name: "store",
operand_kind: OperandKind.RegReg,
encoding: 11,
is_directive: false,
},
[InstructionKind.Stpc]: {
kind: InstructionKind.Stpc,
name: "stpc",
operand_kind: OperandKind.Reg,
encoding: 12,
is_directive: false,
},
Expand Down
6 changes: 3 additions & 3 deletions web_impl/dist/vm.js
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Original file line number Diff line number Diff line change
Expand Up @@ -121,9 +121,6 @@ function executeNextInstruction(lynxMachine) {
case InstructionInfo[InstructionKind.Ge].encoding:
lynxMachine.r0 = Number(lynxMachine[reg1] > lynxMachine[reg2]);
break;
case InstructionInfo[InstructionKind.Le].encoding:
lynxMachine.r0 = Number(lynxMachine[reg1] < lynxMachine[reg2]);
break;
case InstructionInfo[InstructionKind.Shift].encoding:
const signBit = (imm & 0b1000) >> 3;
const shiftAmount = imm & 0b0111;
Expand Down Expand Up @@ -151,6 +148,9 @@ function executeNextInstruction(lynxMachine) {
case InstructionInfo[InstructionKind.Store].encoding:
lynxMachine.data[lynxMachine[reg2]] = lynxMachine[reg1];
break;
case InstructionInfo[InstructionKind.Stpc].encoding:
lynxMachine.data[lynxMachine[reg1]] = lynxMachine.pc + 2;
break;
// Jumps
case InstructionInfo[InstructionKind.Jmp].encoding:
// Interpret imm as 4-bit signed (-8 to 7)
Expand Down
18 changes: 9 additions & 9 deletions web_impl/spec.html
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Original file line number Diff line number Diff line change
Expand Up @@ -69,15 +69,15 @@ <h1>The Lynx 8-bit Machine Specification</h1>
| add | 0001 | Reg Reg | r0 = op1 + op2 |
| sub | 0010 | Reg Reg | r0 = op1 - op2 |
| ge | 0011 | Reg Reg | r0 = op1 > op2 (1 if true else 0) |
| le | 0100 | Reg Reg | r0 = op1 < op2 (1 if true else 0) |
| inc | 0101 | Reg | op1 = op1 + 1 |
| dec | 0110 | Reg | op1 = op1 - 1 |
| shift | 0111 | Imm | r0 = r0 << imm with some nuance |
| ali | 1000 | Imm | r0 = r0 & imm |
| li | 1001 | Imm | r0 = imm |
| mv | 1010 | Reg Reg | op1 = op2 |
| load | 1011 | Reg Reg | op1 = mem$op2$ |
| store | 1100 | Reg Reg | mem$op2$ = op1 |
| inc | 0100 | Reg | op1 = op1 + 1 |
| dec | 0101 | Reg | op1 = op1 - 1 |
| shift | 0110 | Imm | r0 = r0 << imm with some nuance |
| ali | 0111 | Imm | r0 = r0 & imm |
| li | 1000 | Imm | r0 = imm |
| mv | 1001 | Reg Reg | op1 = op2 |
| load | 1010 | Reg Reg | op1 = mem\[op2\] |
| store | 1011 | Reg Reg | mem\[op2\] = op1 |
| stpc | 1100 | Reg | mem\[op1\] = pc + 2 |
| jmp | 1101 | Imm | pc = imm |
| jiz | 1110 | Reg Reg | if op2 = 0 then pc = pc + op1 |
| jaiz | 1111 | Reg Reg | if op2 = 0 then pc = op1 |
Expand Down
26 changes: 13 additions & 13 deletions web_impl/src/isa.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@ enum InstructionKind {
Inc,
Dec,
Ge,
Le,
// 4 bit immdiate. If the most significant bit is 1 then right shift, else left shift.
// Shift amount is the remainding 3 bits.
Shift,
Expand All @@ -16,6 +15,7 @@ enum InstructionKind {
Mv, // dest, src
Load, // dest, src
Store, // dest, src
Stpc, // store pc + 2

Jmp, // 4bit jump
Jiz,
Expand Down Expand Up @@ -85,53 +85,53 @@ const InstructionInfo: Record<InstructionKind, Instruction> = {
encoding: 5,
is_directive: false,
},
[InstructionKind.Le]: {
kind: InstructionKind.Le,
name: "le",
operand_kind: OperandKind.RegReg,
encoding: 6,
is_directive: false,
},
[InstructionKind.Shift]: {
kind: InstructionKind.Shift,
name: "shift",
operand_kind: OperandKind.Imm,
encoding: 7,
encoding: 6,
is_directive: false,
},
[InstructionKind.Ali]: {
kind: InstructionKind.Ali,
name: "ali",
operand_kind: OperandKind.Imm,
encoding: 8,
encoding: 7,
is_directive: false,
},
[InstructionKind.Li]: {
kind: InstructionKind.Li,
name: "li",
operand_kind: OperandKind.Imm,
encoding: 9,
encoding: 8,
is_directive: false,
},

[InstructionKind.Mv]: {
kind: InstructionKind.Mv,
name: "mv",
operand_kind: OperandKind.RegReg,
encoding: 10,
encoding: 9,
is_directive: false,
},
[InstructionKind.Load]: {
kind: InstructionKind.Load,
name: "load",
operand_kind: OperandKind.RegReg,
encoding: 11,
encoding: 10,
is_directive: false,
},
[InstructionKind.Store]: {
kind: InstructionKind.Store,
name: "store",
operand_kind: OperandKind.RegReg,
encoding: 11,
is_directive: false,
},
[InstructionKind.Stpc]: {
kind: InstructionKind.Stpc,
name: "stpc",
operand_kind: OperandKind.Reg,
encoding: 12,
is_directive: false,
},
Expand Down
6 changes: 3 additions & 3 deletions web_impl/src/vm.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -150,9 +150,6 @@ function executeNextInstruction(lynxMachine: LynxMachine): boolean {
case InstructionInfo[InstructionKind.Ge].encoding:
lynxMachine.r0 = Number(lynxMachine[reg1] > lynxMachine[reg2]);
break;
case InstructionInfo[InstructionKind.Le].encoding:
lynxMachine.r0 = Number(lynxMachine[reg1] < lynxMachine[reg2]);
break;
case InstructionInfo[InstructionKind.Shift].encoding:
const signBit = (imm & 0b1000) >> 3;
const shiftAmount = imm & 0b0111;
Expand All @@ -179,6 +176,9 @@ function executeNextInstruction(lynxMachine: LynxMachine): boolean {
case InstructionInfo[InstructionKind.Store].encoding:
lynxMachine.data[lynxMachine[reg2]] = lynxMachine[reg1];
break;
case InstructionInfo[InstructionKind.Stpc].encoding:
lynxMachine.data[lynxMachine[reg1]] = lynxMachine.pc + 2;
break;
// Jumps
case InstructionInfo[InstructionKind.Jmp].encoding:
// Interpret imm as 4-bit signed (-8 to 7)
Expand Down