Digital Platform

the purpose of this platform is two folds:

• make FPGA and system design easier
• validate reflow at a bigger scale

digital blocks

internal bus

• abus
• ports
• sram

basic

• adder_cla
• adder_rca
• comp_eq
• comp_gt
• comp_lt
• gray_counter
• multiplier_booth_4
• multiplier_comb
• resync + clock mux

signal processing

• fir
• sinus
• cosinus
• viterbi decoder

tests

• fcounter
• jtag_sib
• jtag_tdr
• jtag_fsm
• oscillator
• timer

mixed-mode

• adc_sar