Expose coherent allocator accounting and correct quantized bias sums

[Gajesh2007]

Admission accounting currently combines independent allocator counter reads and logical buffer sizes. Concurrent allocator activity can produce an incoherent snapshot, while alignment and cached-buffer reuse can make the real backing larger than the requested payload.

This change adds a coherent native memory snapshot, checked per-allocation footprint bounds, and a detached immutable sizing policy. Metal, CPU and CUDA expose the corresponding interfaces; the allocator's existing allocation/reuse behavior remains the authority. These APIs describe allocator accounting, not process RSS or a promise of immediately available physical memory.

The quantized-vector correction promotes every bias-sum operand to the accumulator type in load_vector and load_vector_safe. Its companion Swift update regenerates both embedded shader sources; replacing only the metallib is insufficient.

Before

flowchart LR
  Caller[Admission caller] --> Counters[Separate active / cache / peak reads]
  Caller --> Logical[Requested logical bytes]
  Logical --> Allocator[Allocator alignment and buffer reuse]
  Counters --> Estimate[Potentially inconsistent accounting]
  Allocator --> Estimate
  QMV[Affine quantized vector] --> Narrow[load_vector sums narrow operands before promotion]

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After

flowchart LR
  Caller[Admission caller] --> Snapshot[get_memory_snapshot under one allocator lock]
  Caller --> Policy[Capture immutable AllocationFootprintPolicy]
  Policy --> Bound[Checked scalar upper bound before allocation]
  Bound --> Allocator[Existing allocator and reuse rules]
  Snapshot --> Accounting[Coherent counters plus explicit footprint contract]
  Allocator --> Accounting
  QMV[Affine quantized vector] --> Promote[load_vector and safe variant promote each operand]
  Promote --> Sum[Accumulator-type bias sum]

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Reviewed source and signed publication

• Reviewed source: fab0f39f69140393b454c32d6f4bf7a9b32f9dcc.
• Signed publication head: f8eec2476cdb5263fb6e2a19dd71f2c8b7c0a7d3 on release/0.9.0-validation.
• This existing signed head is retained because its source tree is already current; no empty commit was added.
• Normalizing only the signed dependency pins recovers the exact reviewed source tree. Both parent Vercel suppressions remain branch-specific.

Validation and its scope

• The corrected GPU operator discriminator lane passed 216/216 cases after regenerating embedded JIT shader text and relinking. Both the original and metallib-only attempts retained 156/216 exact cases; those failed discriminators remain recorded.
• The corrected runtime artifact passed root source/resource/build-output review. That review did not run full models and is not release certification.
• Earlier allocator evidence used core 560f57ccc1e42cb451651976363764a5033c8c95: four CPU and four Metal policy cases, 20,000 coherent snapshot transfers, and a negative control that reproduced inconsistent independent reads. The older combined 83-function/100-case lane and metallib 47357f1b... remain baseline evidence, not a test of this corrected kernel.
• The quantized change affects accumulator promotion in both vector loaders; host dispatch logic, cache/attention policy and capacity are unchanged. The full upstream suite and CUDA path are not claimed as executed.

Frozen Gemma controls and their limits

• On the reviewed 53f3c3d0 / native de30ef98 / Swift c06149b4 / core fab0f39f runtime, cache-off B1 Gemma QAT4 is now exact across contiguous and paged backends in ordinary, automatic and serial-target modes. Serial-target also matches ordinary.
• Automatic still differs from ordinary on both backends at zero-based index 30. The whole-verifier comparison therefore remains a failure/open gate. These seven complete trajectories reuse one fixture prompt; they are not seven independent quality prompts.
• The later recurrent-teacher runtime is outside those frozen model controls. No new throughput, B2/B4, SSD-hit, pressure, fleet-model or 0.9.0 default-posture result is inferred from them.

Remaining gates — keep draft

• Full-model, whole-verifier and 0.9.0 default/release gates remain open. In particular, Gemma automatic-versus-ordinary index 30 and the outstanding Qwen trajectory/state investigations are not waived by backend equality or operator proximity.
• Complete the exact fleet-model/backend/cache/MTP matrix, capacity/co-residency and pressure coverage, uncontended B1/B2/B4 comparisons, connected/two-host recovery and persistent-key restart evidence on the final bound artifacts.
• Complete full provider CI compilation and GPU regression for the public-API test fix, applicable platform review, and immutable signed-artifact checks. CUDA execution remains outside the macOS evidence. Historical failed checks are preserved; no new full-suite pass is claimed here.
• Explicit release, deployment, signing-workflow activation/dispatch and benchmark approval remain separate. Both Vercel configs suppress only release/0.9.0-validation. No production budget, equality criterion or tolerance is relaxed.

Companion review stack

Draft PR	Signed head	Reviewed source
mlx #15	f8eec2476cdb5263fb6e2a19dd71f2c8b7c0a7d3	fab0f39f69140393b454c32d6f4bf7a9b32f9dcc
mlx-c #8	8bdeb0f3c5793c54139e86c5437b09abc9ab9b42	d4328f2d8d54d711d5419e07ab9fa2f07b512a48
mlx-swift #21	c3ac44766c3e0be2066bbd87a3e26aaa6f410ab0	9561227d55a07db29f70a78aadc5d6b5aaeb10bf
mlx-swift-lm #141	67ac8607b5846e8acfbbdd8f36c0d252d69d0d01	ba5c03ea0ef495aca02c99c7a2dd2b7a32bc7668
d-inference #851	e1d68db84cb1a1e4a6dd10306383bd64bc5d6062	d01b82078e157ae1e66511d2d8db1f2ecf95e857

Evidence navigation

Reports retain their original source, artifact and result identities. Current links are pinned to this signed parent publication.

• Strict validation procedures.
• Recurrent teacher state and peak-capacity evidence.
• Corrected Gemma backend controls and remaining verifier failure.
• Allocator footprint and backing ownership.
• Qwen common-input operator evidence.
• Two-host fixture evidence.