References
[1] Skolnik, M. I., Introduction to Radar Systems, 3rd ed., Boston, MA: McGraw Hill, 2001.
[2] Mankins, J. C., “Technology Readiness Levels,” White Paper, April 6, 1995, https://aiaa.kavi.com/apps/group_public/download.php/2212/TRLs_Mankins-Paper_1995.pdf.
[3] Taleb, N. N., The Black Swan: The Impact of the Highly Improbable, New York: Random House, 2007.
[4] Koch, D., FPGAs for Software Programmers, New York: Springer Science+Business Media, 2015.
[5] Goldsmith, J., et al., “Control and Visualisation of a Software Defined Radio System on the Xilinx RFSoC Platform Using the PYNQ Framework,” IEEE Access, Vol. 8, 2020, pp. 129012–129031.
[6] Gaide, B., et al., “Xilinx Adaptive Compute Acceleration Platform:VersalTM Architecture,” Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, 2019.
[7] Manz, B., “The RFSoC Upends the Design Paradigm,” The Journal of Electronic Defense, August 2019, pp. 20–24.
[8] Amazon, “F1 Instances: Run Custom FPGAs in the Amazon Web Services (AWS) Cloud,” https://aws.amazon.com/ec2/instance-types/f1/, 2017.
[9] Liguori, A., and Amazon, “IEEE Hot Chips 2019 Tutorial: The Nitro Project – Next Generation AWS Infrastructure,” 2019, https://old.hotchips.org/hc31/HC31_T1_AWS_Nitro_Hot_Chips_20190818-2.pdf.
[10] Chiou, D., et al., “IEEE Hot Chips 2019 Tutorial: Cloud Acceleration at Microsoft,” 2019, https://old.hotchips.org/hc31/HC31_T2_Microsoft_CarrieChiouChung.pdf.
[11] Chao, C., B. Saeta, and Google. “IEEE Hot Chips 2019 Tutorial: Cloud TPU: Codesigning Architecture and Infrastructure,” 2019, https://old.hotchips.org/hc31/HC31_T3_Cloud_TPU_Codesign.pdf.
[12] Shalev, L., et al., “Supercomputing on Nitro in AWS Cloud,” IEEE Micro, 2020, pp. 1-1.
[13] Chung, E., et al., “Serving DNNs in Real Time at Datacenter Scale with Project Brainwave,” IEEE Micro, Vol. 38, No. 2, 2018, pp. 8–20.
[14] Wang, Y. E., G. -Y. Wei, and D. Brooks, “Benchmarking TPU, GPU, and CPU Platforms for Deep Learning,” arXiv preprint arXiv:1907.10701, 2019. https://arxiv.org/abs/1907.10701 (see https://github.com/LVFPGABOOK/Chapter-3-Background-Technology/commit/ea5e134990e5f1892f74107c7311702310e24050).
[15] Khokhar, A. A., et al., “Heterogeneous Computing: Challenges and Opportunities,” Computer, Vol. 26, No. 6, 1993, pp. 18–27.
[16] Mittal, S., and J. S. Vetter, “A Survey of CPU-GPU Heterogeneous Computing Techniques,” ACM Comput. Surv., Vol. 47, No. 4, 2015, Article 69.
[17] Nane, R., et al., “A Survey and Evaluation of FPGA High-Level Synthesis Tools,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No. 10, 2016, pp. 1591–1604.
[18] Aktemur, B., et al., “Debugging SYCL Programs on Heterogeneous Intel® Architectures,” Proceedings of the International Workshop on OpenCL, 2020, pp. 1–10.
[19] Gershon, R. A., “Innovation Failure: A Case Study Analysis of Eastman Kodak and Blockbuster Inc,” in Media Management and Economics Research in a Transmedia Environment, Routledge, 2013, pp. 62–84.
[20] Lewis, R., “Unifying MSc Physics and MSc Astrophysics Problem-Based Learning with LabVIEW NXG: A Critical Review,” Instruments Academic User Forum 2019, University of Birmingham, Birmingham, UK, 18 January 2019, http://orca.cf.ac.uk/118881/ (http://orca.cf.ac.uk/118881/1/2019-01-18_ni_academic_users_forum.pdf and https://github.com/LVFPGABOOK/Chapter-6-Looking-Ahead/commit/8a322734bb0bb4dbec7ff6c2d17eadb6834cdc06).
[21] Mikhaylov, V. Y., and R. B. Mazepa, “USRP Devices Application for Modeling Signal-Like Interference in Wireless Networks,” 2020 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO), July 1–3, 2020, pp. 1–6.
[22] Mikhaylov, V. Y., and R. B. Mazepa, “Research of Cognitive Radio Technology Application Cases in the Tasks of Providing Information Needs,” 2020 Wave Electronics and Its Application in Information and Telecommunication Systems (WECONF), June 1–5, 2020, pp. 1–7.
[23] Waterman, A., et al., The RISC-V Instruction Set Manual, Volume I: Base User Level ISA, EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62, Vol. 116, 2011, http://www.icsi.berkeley.edu/pubs/arch/EECS-2011-62.pdf.
[24] Ryzhyk, L., “The ARM Architecture,” Chicago University, Illinois, EUA, 2006, https://www.researchgate.net/profile/Leonid_Ryzhyk/publication/228392292_The_ARM_Architecture/links/554b73c40cf29f836c96b2b7.pdf.
[25] Gray, J., “GRVI Phalanx,” January 5, 2016, https://riscv.org//wp-content/uploads/2016/01/Tues1215-RISC-V-Gray-GRVI-Phalanx-final-final.pdf.
[26] Gray, J., “2GRVI Phalanx: W.I.P. Towards Kilocore RISC-V® FPGA Accelerators with HBM2 DRAM,” IEEE Hot Chips 2019 Conference poster, Bellevue, WA, 2019, https://old.hotchips.org/hc31/HC31.GrayResearch.JanGray.v01.pdf.
[27] Kathail, V., “Xilinx Vitis Unifi ed Software Platform,” The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, 2020.
[28] Kova, M., et al., “How Europe Is Preparing Its Core Solution for Exascale Machines and a Global, Sovereign, Advanced Computing Platform,” Mathematical and Computational Applications, Vol. 25, No. 3, 2020, p. 46.
[29] Griffi ths, H., et al., Stimson’s Introduction to Airborne Radar, 3rd ed., Edison, NJ: SciTech Publishing, 2014.
[30] Guerci, J. R., Cognitive Radar: The Knowledge-Aided Fully Adaptive Approach, Norwood, MA: Artech House, 2010.
[31] Walsh, E., and I. Cho, “Using Evernote as an Electronic Lab Notebook in a Translational Science Laboratory,” Journal of Laboratory Automation, Vol. 18, No. 3, 2013, pp. 229–234.
[32] NI, NI LabVIEW High-Performance FPGA Developer’s Guide, 2014, p. 94, http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf.
[33] O’Donnell, R. M., “Introduction to Radar Systems YouTube playlist,” July 25, 2018, https://www.youtube.com/playlist?list=PLUJAYadtuizA8RC2Qk8LfmiWA56HZsk9y.
[34] O’Leary, D. E., “Gartner’s Hype Cycle and Information System Research Issues,” International Journal of Accounting Information Systems, Vol. 9, No. 4, December 1, 2008, pp. 240–252.