Popular repositories Loading

1. simtix simtix Public

   GPU-inspired SIMT accelerator attached to a 5-stage RISC-V processor (SystemVerilog, Verilator)

   SystemVerilog 1

2. 5-stage-pipelined-riscv 5-stage-pipelined-riscv Public

   Synthesizable 5-stage pipelined RISC-V (RV32I) processor in Verilog. Verified in Vivado 2025.1 through post-implementation functional sim on XC7A200T. Timing met @ 83.33 MHz.

   Verilog 1

3. mesi-cache-coherence mesi-cache-coherence Public

   Snooping MESI cache-coherence unit for a multicore system (SystemVerilog)

   SystemVerilog

4. async-fifo-cdc async-fifo-cdc Public

   Parameterisable dual-clock FIFO in SystemVerilog: Gray-pointer CDC, bound SVA, 8-config self-checking regression (xsim + Icarus), and the Vivado CDC constraints. Placed and routed on ZCU104.

   SystemVerilog

5. riscv-cache-extension riscv-cache-extension Public

   Open-source RTL reproduction of 'Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC' (Kamaleldin et al., IEEE SOCC 2024): a snoop-coherent private L1 data-cache sub-system for in-order R…

   SystemVerilog