- A feedback-driven adaptive learning binary-classifier that based on error input autonomously alters its decision boundary by implementing Max-Initialized Decremental Search (MIDS) and State Aware Threshold Update (SATU) and resetting the control loop for repeated adaptive cycles.
🤖 Adaptive learning system implementing MIDS algorithm
🤖 Adaptive learning system implementing SATU algorithm
- Stage 0 (v0.x): Strict Boolean pattern relation analyzer. No learning, no noise tolerance, decision boundaries fixed by structural wiring.
- Stage 1 (v1.0): Popcount based similarity and a variable threshold to alter the decision boundary. Introduces noise tolerance and ability to change the decision output without structural changes.
- Stage 2 (v1.1): Cybernetic Feedback-driven adaptive learning. System alters its decision boundary based on external feedback to correct its decision output.
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Version 0: A pattern relation analyzer that classifies how an input pattern relates to a stored pattern, enforces rule based recognition rather than learning.- Detector_v0.0 -> Recognizes the exact pattern and sub-patterns if they are inside the boundary set up by weights-grid.
- Detector v0.1 -> Recognizes the exact pattern and super-patterns if they are outside the boundary set up by weights-grid.
- Detector v0.2 -> Classifies the input as a sub-pattern, super-pattern, anti-pattern or equivalence precisely through a 2-POV logical analysis.
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Version 1: Pop-count based judgement against a variable Threshold instead of perfect equivalence check and cybernetic feedback-driven adaptive learning.- Detector_v1.0 -> Recognizes the pattern if total number of matched pixels are greater than the set threshold which can vary giving us ability to control the decision output.
- Detector_v1.1 -> A feedback-driven adaptive system that autonomously adjusts its decision boundary to correct its output, using algorithms optimized for hardware constraints.
🧩 Block Diagram - Detector_v1.0 (Manually Alterable Decision Boundary)
| Property | MIDS | SATU |
|---|---|---|
| Correction Speed | O(N) | O(1) |
| State Awareness | None | Current & desired output |
| Correction Strategy | Iterative threshold traversal | Direct threshold computation |
| Direction | Starts from maximum threshold and decrements | Computes T = M−1 or T = M directly |
| Threshold Storage | Requires threshold memory | No threshold memory required |
| Traversal Logic | Required | Not required |
| Synchronization | Multiple synchronization requirements | Single synchronizer |
| Control Hardware | Large control loop coordinating traversal | Simpler control path |
| Initialization | threshold memory programming | No Initialization Required |
| Hardware Complexity | Higher | Lower |
| Setup Complexity | Higher | Very low |
| Convergence | Yes, for M ∈ {1,...,15} | Yes, for M ∈ {1,...,15} |
| Algorithmic Principle | Search for the boundary | Compute the boundary |
⏱️ Correction Speed Complexity Comparison
Equivalence & Sub-Pattern Recognition 🔹
Equivalence & Super-Pattern Recognition 🟦
Equivalence & Super & Sub & Anti-Pattern Recognition 🔹🟦
Manually Alterable Decision Boundary ⚖️
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🤖 Automatic Decision Boundary Alteration - MIDS
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🤖 Automatic Decision Boundary Alteration - SATU
To verify hardware realizability, all detector variants were synthesized using Yosys, technology mapped to the Sky130HD standard-cell library, and analyzed using static timing and power estimation. The resulting gate-level netlists were used to compare architectural complexity, silicon area, timing characteristics, power consumption, and estimated operating frequency across the evolution of the Cybernetic Classifier.
Technology: Sky130HD
| Version | Module | Area | Critical Path Delay | Power |
|---|---|---|---|---|
| Detector v0.0 | Eq/Sub Recognizer | 127.6224 µm² | 0.46 ns | 30.8 µW |
| Detector v0.1 | Eq/Super Recognizer | 127.6224 µm² | 0.46 ns | 30.8 µW |
| Detector v0.2 | Multi-POV Classifier | 230.2208 µm² | 1.16 ns | 60.6 µW |
| Detector v1.0 | Pop-Count Recognition | 970.9312 µm² | 4.58 ns | 599 µW |
| Detector v1.1 | MIDS | 1244.944 µm² | 1.76 ns | 833 µW |
| Detector v1.1 | SATU | 1178.6304 µm² | 2.09 ns | 1.10 mW |
| Category | Result |
|---|---|
| Smallest Design | Eq/Sub & Eq/Super Recognizers (127.62 µm²) |
| Largest Design | MIDS (1244.94 µm²) |
| Fastest Design | Eq/Sub & Eq/Super (0.46 ns) |
| Slowest Design | Pop-Count Recognition (4.58 ns) |
| Lowest Power | Eq/Sub & Eq/Super (30.8 µW) |
| Highest Power | SATU (1.10 mW) |
| Fastest Adaptive Design | MIDS (1.76 ns) |
| MIDS Timing Slack | 8.11 ns @ 10 ns clock |
| SATU Timing Slack | 7.79 ns @ 10 ns clock |
| MIDS Fmax | ≈568 MHz |
| SATU Fmax | ≈478 MHz |
| Most Arithmetic-Heavy | Pop-Count Recognition (15 Adders) |
| Most Decision-Heavy | Multi-POV Classifier (11 MUXes) |
| Largest Cell Count | Multi-POV Classifier (28 cells) |
Detector_v0.2 Synthesized - Yosys
The current architecture demonstrates adaptation without persistent memory. When feedback indicating an incorrect decision, the system modifies its internal threshold state, thereby changing its future decision boundary. This change of state in response to feedback is the adaptation mechanism itself, persistent memory is not a prerequisite for adaptive behavior.
A possible extension is memory-assisted retention, where the input/reference pattern and its learned threshold are stored in memory. When the same or a previously encountered pattern appears again, the corresponding threshold could be retrieved rather than relearned. This would allow the system to retain multiple learned states across different patterns.
Thus, the two concepts are distinct:
- Adaptation: changing the system's state in response to feedback.
- Retention: preserving that adapted state for later retrieval.
The current project focuses deliberately on adaptation and cybernetic feedback, while persistent retention is left as a possible architectural extension.
- Source code and HDL files are licensed under the MIT License.
- Documentation, diagrams, images, and PDFs are licensed under Creative Commons Attribution 4.0 (CC BY 4.0).