Additional device entries for the LG.DAT logic test library used by
EE Tools Max Loader device programmers
(TopMax, TopMax II, ChipMax, ChipMax2, UniMax, ProMax).
Max Loader ships with a library of TTL and CMOS logic test vectors, but its coverage of older bipolar memory, static RAM, and bus interface devices is thin. This repository adds entries for parts commonly found in arcade, pinball, and vintage computer hardware.
LG.DAT is a plain text file in the Max Loader installation directory, by
default:
%ProgramFiles(x86)%\EETools
Each device is declared with a header line giving the part name and its DIP pin count, followed by one test vector per line. Within a vector, character position corresponds to physical pin number, counting from pin 1.
| Character | Meaning |
|---|---|
0 / 1 |
Programmer drives the pin low / high |
L / H |
Programmer expects to read a low / high level |
Z |
Programmer expects a high-impedance or undriven pin |
X |
Don't care, pin is not tested |
C |
Clock pulse |
G |
Ground |
V |
Vcc |
Lines use CRLF endings. A vector must contain exactly as many characters as the
pin count declared in its header. Note that G and V are not always on the
last two pins: the 1489 places ground on pin 7, and parts such as the 7473 place
Vcc mid-package.
| File | Type | Size | Contents |
|---|---|---|---|
LG.DAT.RAM |
Complete library | 54 KB | Static and bipolar RAM tests for the 82S09, 6116, and 93422 |
LG.DAT.KLOV |
Add-on set | 23 KB | 16 memory and bus interface entries collected from the Arcade Museum (KLOV) community thread |
LG.DAT.RAM is a complete replacement library. LG.DAT.KLOV is a set of
additional entries intended to be appended to your existing library, not to
replace it. See the installation notes for each below.
Back up your original library before doing anything else.
Close Max Loader before modifying LG.DAT. The file is read at startup, so
changes do not take effect until the software is restarted.
- Navigate to the installation directory listed above.
- Rename the existing
LG.DATtoLG.DAT.Original. - Copy
LG.DAT.RAMinto that directory. - Rename it to
LG.DAT. - Start Max Loader. The new devices appear in the device selection list.
To restore factory behaviour, rename LG.DAT.Original back to LG.DAT.
These entries supplement the stock library rather than replacing it. Append the
contents of LG.DAT.KLOV to the end of your existing LG.DAT using a text
editor that preserves CRLF line endings. The combined file lands around 47 KB,
comfortably inside the size limit described below.
Renaming LG.DAT.KLOV to LG.DAT outright will work, but you will lose the
entire stock 7400-series library in the process.
| Entry | Device | Package | Function | Vectors |
|---|---|---|---|---|
.82S09 |
Signetics 82S09 / 82S19 | 28-pin DIP | 64 x 9 bipolar RAM, inverting, open collector | 519 |
.6116 |
6116 and compatibles | 24-pin DIP | 2K x 8 static RAM, three-state | 519 |
.93422 |
AMD Am93422 and compatibles | 22-pin DIP | 256 x 4 bipolar RAM, noninverting, three-state | 1065 |
Validation status. All three entries have been confirmed on hardware against both known-good and known-faulty devices. Good parts pass and faulty parts are correctly rejected.
Coverage. Each entry opens with a settle preamble and a set of memory-independent chip-disable checks, so a device that is unpowered or incorrectly seated fails within the first few vectors rather than partway through the array. A walking-bit section at a fixed address then verifies the data path one bit at a time. The main body writes the array and reads it back in a separate read-only pass, which is what gives genuine address decoder coverage.
Device compatibility notes.
- The 82S19 uses the same vector set as the 82S09. The two parts differ only
in whether the outputs blank during a write cycle, and the outputs are marked
don't-care during writes, so that difference is never exercised. Select
82S09when testing an 82S19. - The 93412 is the open-collector member of the 93422 family and shares its
pinout. To convert, replace every
HwithZinside the.93422block and rename the entry.Happears nowhere except as an expected output level, so a find-and-replace scoped to that block is the entire change.
| Entry | Device | Package | Function | Vectors |
|---|---|---|---|---|
.8216 |
Intel 8216 | 16-pin DIP | 4-bit bidirectional bus driver | 12 |
.29701 |
AMD Am27901 (see naming note) | 16-pin DIP | 16 x 4 bipolar RAM, noninverting | 64 |
.7489 |
7489 | 16-pin DIP | 16 x 4 bipolar RAM, inverting, open collector | 64 |
.74189 |
74189 | 16-pin DIP | 16 x 4 bipolar RAM, inverting, three-state | 64 |
.82S16 |
Signetics 82S16 | 16-pin DIP | 256 x 1 bipolar RAM | 1024 |
.25S09 |
AMD Am25S09 | 16-pin DIP | Quad 2-input high-speed register | 4 |
.8212 |
Intel 8212 | 24-pin DIP | 8-bit I/O port, three-state | 13 |
.8T95 |
8T95 | 16-pin DIP | Hex buffer, noninverting, three-state | 4 |
.8T96 |
8T96 | 16-pin DIP | Hex buffer, inverting, three-state | 4 |
.8T97 |
8T97 | 16-pin DIP | Hex buffer, noninverting, three-state | 11 |
.8T98 |
8T98 | 16-pin DIP | Hex buffer, inverting, three-state | 6 |
.8T28 |
8T28 | 16-pin DIP | Quad bus transceiver, three-state | 6 |
.8T38 |
8T38 | 16-pin DIP | Quad bus transceiver | 6 |
.26LS31 |
AMD Am26LS31 | 16-pin DIP | Quad differential line driver, three-state | 5 |
.26LS33 |
AMD Am26LS33 | 16-pin DIP | Quad differential line receiver, three-state | 5 |
.1489 |
1489 | 14-pin DIP | Quad line receiver, ground on pin 7 | 2 |
Several of these entries cover more than one part number. Rather than duplicating vectors, either remember the equivalence or copy the block and rename it so the part appears under its own name in the device list.
16 x 4 bipolar RAM. The .7489 entry also tests the 74289, AMD Am27LS02,
Intel P3101A, and 82S25. These are functionally identical for testing purposes.
Signetics 82S16. The .82S16 entry also tests the Fairchild 93321.
Motorola 68xx bus interface parts. Useful if you work on 6800-based systems:
| Signetics | Motorola |
|---|---|
| 8T28 | MC6889 |
| 8T96 | MC6886 |
| 8T97 | MC6887 |
| 8T98 | MC6888 |
The originating forum post describes this device as the AM27901, but the
entry is named .29701. One of the two has transposed digits, and the source
material does not resolve which. The vectors themselves are unambiguous: writing
a 0 reads back L and writing a 1 reads back H, confirming non-inverting
outputs as described. The entry name has been left as published. Verify the part
number on your device before relying on it.
For reference, the TTL part with the same organization and non-inverting outputs is the 74219.
Two constraints are worth knowing about before you write your own entries. Neither is documented by the vendor, and both cost real debugging time to find.
ml.exe parses LG.DAT into a fixed buffer. Exceeding roughly 65,536 bytes
produces a null-pointer dereference rather than a graceful error:
Access violation at address 00526263 in module 'ml.exe'. Read of address 00000000.
The failure occurs at load time, not at test time, and the offending entry is not identified. If you see this dialog after editing the library, check the file size first. This is why device families here are distributed as separate libraries rather than as one combined file.
The programmer applies each vector by updating its pin drivers, with no
guarantee about the relative order in which individual pins settle. If the
address bus changes state while /WE is asserted, the device writes to whatever
intermediate addresses the bus passes through, silently corrupting locations
that were never targeted.
Every write in the LG.DAT.RAM entries is therefore a three-vector sequence:
0000000001111G0XXXXXXXXX000V address and data set, /WE high
0000000001110G0XXXXXXXXX000V /WE pulsed low, address already stable
0000000001111G0XXXXXXXXX000V /WE returned high before the address moves
The address is only ever allowed to change while /WE is high. A single
unguarded write is enough to fail a test, including the very first vector of an
entry, where the device may still be settling after power is applied.
With this in place, a write-all-then-read-all structure is safe, and the readback pass provides address decoder coverage that a simple write-then-verify-immediately pattern cannot.
The older LG.DAT.KLOV RAM entries take the alternative approach of writing and
verifying each address immediately, which tolerates the glitch but cannot detect
address aliasing. Both approaches are valid; they trade coverage against vector
count.
All entries in this repository have been checked programmatically for
structural correctness: every vector matches its declared pin count, uses only
valid characters, and places G and V on consistent pins throughout its
entry.
Structural validity is not the same as functional correctness, so the
LG.DAT.RAM entries have additionally been validated on hardware against both
known-good and known-faulty devices.
Testing against a failing device matters as much as testing against a working one. A vector set that is too permissive passes every part put in front of it, and a vector set containing an error fails every part regardless of condition. Neither fault is visible if you only ever test known-good silicon.
The LG.DAT.KLOV entries are reproduced as published and have not been
independently re-verified here.
The LG.DAT.KLOV entries were contributed by channelmanic in the Arcade
Museum forum thread
Adding chips to Max Loader,
along with the accompanying part equivalence notes reproduced above.
These entries are provided as-is. Verify any pinout against the manufacturer
datasheet before use, and keep a backup of your original LG.DAT. Testing a
device with an incorrect vector set can damage it.
Additional device entries are welcome. Please include the manufacturer and part number, the package and pin count, a note on whether the outputs are three-state or open collector, and confirmation that the entry has been validated against a known-good device.