Digital Safe (Verilog FPGA Project)

System description

This project implements a digital safe using Verilog on FPGA.

Features

• Four digits pasword.
• Visual & audio communication of the safe & password status with the user.

INPUTS

• 4-Switches to input each digits values on 4bits from 0 to F
• 3-Buttons to operate the system by the user Button-Up) Reset the system, Button-Center) Relock the safe, Button-Down) Confirm current digit input by the switches.

OUTPUTS

• 4x7-Segments displays : Displays the LOCK/OPEN status.
• 4x7-Segments displays : Displays the current digit input value and password completion of each digits.
• 2xDebug LEDs : LED n°8 flag lock status of the safe, LED n°7 keep tracks of the error flag.
• RGB LED : A user friendly way to indicate the OPEN/LOCK/Err status to the user thanks to color code ( where GREEN : OPEN / RED : LOCK / BLUE : Err). OPEN : Digital safe is unlocked, LOCK : Digital safe is locked, Err : Wrong password input.
• Relay : Emit a sound when changing state from OPEN to LOCK

USER MANUAL

1. Reset the system to start a new input
2. Compsoe the first digit with the switchs
3. Confirm the digit value input
4. Repeat until the 4th digit
5. When confirming the 4th digit the system should display the safe OPEN/CLOSE/Err status.

Author & Roles

• John Heshmat [Password matching comparaison]
• Peter Shehata [Openning/Locking system]
• Maxime Lecomte [Input conversion block]

Project poster

Digital Safe Poster.pdf

Project video demonstration

Block diagram

digital_safe_top_tb simulation

digital_safe_top_tb.v

safe_core_tb simulation

safe_core_tb

display_8digit_tb simulation

display_8digiti_tb

Resources_Report