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1. RISC-V_Processor RISC-V_Processor Public

   I built a 5-stage pipelined RISC-V Processor in SystemVerilog.

   SystemVerilog 1

2. Asynchronous_FIFO Asynchronous_FIFO Public

   This repository features an asynchronous FIFO design I built from scratch in SystemVerilog. I include RTL designs, thorough test benching, and documentation.

   SystemVerilog