Platform on FPGA to which heterogeneousRTOS is interfaced to. The project targets a Xilinx Zynq FPGA. The repository contains a Vivado project and the IPs designed in Verilog (the scheduler and the triple modular redundancy voters) by means of HLS (the fault detector) for heterogeneousRTOS project (https://github.com/HEAPLab/heterogeneousRTOS). The repository has been created by @GilgameshJR.