BITSilicon – Digital Design Assignments

This repository is used for assignment submissions.

Submission Instructions

1. Create a folder inside submissions/ with your full name-ID.
2. Inside your folder, add:
   • src/ → all Verilog files
   • docs/ → report / screenshots
   • README.md → brief explanation of your approach
3. Commit all files and push before the deadline.

⚠️ Do not modify or delete other folders.